LPC1113FHN33/301 NXP Semiconductors, LPC1113FHN33/301 Datasheet - Page 29

• Manufacturer Part Number: LPC1113FHN33/301
• Description: MCU, 32BIT, 24KFLASH, CORTEX-M0, 33HVQFN
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/301

• Controller Family/series: ARM Cortex-M0
• No. Of I/o's: 28
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Core Size: 32bit
• Program Memory Size: 24KB
• Oscillator Type: External, Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.16.1 Start logic
7.16.2 Reset
7.16.3 Brownout detection
7.16.4 Code security (Code Read Protection - CRP)
7.16 System control
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in
NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when
the chip is running. In addition, an input signal on the start logic pins can wake up the chip
from Deep-sleep mode when all clocks are shut down.
The start logic must be configured in the system configuration block and in the NVIC
before being used.
Reset has four sources on the LPC1111/12/13/14: the RESET pin, the Watchdog reset,
power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage
attains a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
The LPC1111/12/13/14 includes four levels for monitoring the voltage on the V
this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal
to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
This feature of the LPC1111/12/13/14 allows user to enable different levels of security in
the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC111x user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
Table 3
All information provided in this document is subject to legal disclaimers.
to
Table 5
Rev. 4 — 10 February 2011
as input to the start logic has an individual interrupt in the
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2011. All rights reserved.
DD
pin. If
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