ECOG1XE01A6 CYAN, ECOG1XE01A6 Datasheet - Page 28

• Manufacturer Part Number: ECOG1XE01A6
• Description: IC, 16BIT MCU, ECOG1X, 70MHZ, QFN-68
• Manufacturer: CYAN

Specifications of ECOG1XE01A6

• Controller Family/series: ECOG1X
• No. Of I/o's: 20
• Ram Memory Size: 8KB
• Cpu Speed: 70MHz
• No. Of Timers: 8
• Digital Ic Case Style: QFN
• Core Size: 16 Bit
• Program Memory Size: 64KB
• Embedded Interface Type: I2C, JTAG, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Version 1.15
DUSART
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The DUSART is a general purpose dual synchronous/asynchronous serial port. Each of the two
channels can implement one of the supported protocols. Note that each serial protocol may only be
used once, the same protocol cannot be used simultaneously on both channels (except for the generic
User Serial Port function which can be used on both channels).
The following protocols are supported by the DUSART peripheral.
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UART
The UART implementation within the DUSART peripheral provides all of the common functions
required.
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SPI
SPI is one of the protocols supported by the DUSART peripheral. This gives the eCOG1X both SPI
master and slave capability, with the option of supporting multiple slave devices in master mode.
The SPI function includes the following features.
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I
The Inter-IC Communication standard (I
interface for connecting microcontrollers to their peripheral devices such as memories and interface
ICs. It is capable of serial data transfer up to speeds of 100 kbps (standard), 400 kbps (fast mode) and
3.4 Mbits/s (high speed mode). The DUSART I
The I
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C
Standard UART.
Serial Peripheral Interface (SPI).
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Low rate IrDA and general purpose infrared controller protocol (IFR).
ISO 7816 smart card interface (SCI).
Generic User Serial Port (USR).
Programmable format: 5, 6, 7 or 8 data bits; 1, 1.5 or 2 stop bits, even, odd or no parity.
Programmable baud rate.
8-bit and 16-bit transmit data registers (one and two data frames).
Interrupts generated on transmit ready and overflow.
8-bit and 16-bit receive data register (one and two data frames).
Interrupts generated on one or two bytes received.
Configurable data signal polarities.
Transmit break control.
Receive break interrupt and status bit.
Receive frame error detection interrupt and status bit.
Receive timeout.
Transmit guard time.
Master and slave operation.
Programmable serial clock polarity and phase.
Data transfer size 1 to 16 bits.
Programmable serial clock frequency (master mode).
Up to four chip select outputs (master mode).
Slave mode chip select uses up to four inputs with a pattern match and mask function.
Start, stop, and restart operations.
Address matching and arbitration.
Supports multi-master and master/slave operations.
Automatic acknowledge generation.
7 bit, 10 bit and broadcast addressing.
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C function includes the following features.
C multi-master, multi-drop 2 wire bus.
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
eCOG1X Microcontroller Product Family
www.cyantechnology.com
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C) is a bidirectional, multi-drop, multi-master, two wire
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C function supports 100 kbps operation only.
4 August 2009