ECOG1XE01A6 CYAN, ECOG1XE01A6 Datasheet - Page 74

• Manufacturer Part Number: ECOG1XE01A6
• Description: IC, 16BIT MCU, ECOG1X, 70MHZ, QFN-68
• Manufacturer: CYAN

Specifications of ECOG1XE01A6

• Controller Family/series: ECOG1X
• No. Of I/o's: 20
• Ram Memory Size: 8KB
• Cpu Speed: 70MHz
• No. Of Timers: 8
• Digital Ic Case Style: QFN
• Core Size: 16 Bit
• Program Memory Size: 64KB
• Embedded Interface Type: I2C, JTAG, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Version 1.15
74
Symbol
Symbol
T
T
T
T
t
C
MCLK
R
t
ACLK
SCLK
t
t
N
t
CW
CLK
CD
DH
DS
, t
CK
I2S
The tables below for the I2S function use the following symbols for time periods defined by bit fields in
the I2S configuration registers.
Master mode
M
F
Description
I2S peripheral input clock period
I2S alternate clock input period
I2S master clock period
Master clock divisor
Parameter
I2S serial clock period
SCLK duty cycle (SCLK driven from an internal clock source)
SCLK output rise and fall time
Delay time SCLK falling edge to WS output valid
Delay time SCLK falling edge to data output valid
Setup time data input valid to SCLK rising edge
Hold time SCLK rising edge to data input invalid
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
Table 43: AC characteristics - I2S master mode
Figure 28: I2S master mode timing diagram
eCOG1X Microcontroller Product Family
Table 42: I2S clock symbols
www.cyantechnology.com
clk_sel = 00
clk_sel = 10
mclk_en = 0
mclk_en = 1
mclk_en = 0
mclk_en = 1
mclk_en = 0
mclk_en = 1
Definition
Set by SSM
External input signal
T
T
fd.i2s.cfg2.div_ratio
CLK
ACLK
(T
Min
MCLK
45
21
0
0
0
0
See Table 28
T
/ 2) + 26
MCLK
T
Typ
MCLK
x N
M
Max
4 August 2009
55
2
2
Units
Units
N
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
M