ADC12D040CIVS National Semiconductor, ADC12D040CIVS Datasheet - Page 19

• Manufacturer Part Number: ADC12D040CIVS
• Description: DUAL 12BIT ADC, 40MSPS, SMD, 12D040
• Manufacturer: National Semiconductor

Specifications of ADC12D040CIVS

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Parallel
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.35V To 5.25V, 4.75V To 5.25V
• Sampling Rate: 40MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Applications Information
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
such that the peak excursions of the analog signal does not
go more negative than ground or more positive than 1.0
Volts below the V
generally be about V
V
pins.
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, OEA,
OEB and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 55 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample rate to 100 kSPS.
CM
0 - 0.25V
SIGNAL
RANGE
0 - 0.5V
0 - 1.0V
±
TABLE 3. Resistor Values for Circuit of Figure 5
±
sources as long as no d.c. current is drawn from these
0.25V
0.5V
140Ω
255Ω
464Ω
845Ω
845Ω
A
R1
supply voltage. The nominal V
REF
/2. V
768Ω
768Ω
768Ω
499Ω
499Ω
R2
RM
A and V
226Ω
976Ω
976Ω
845Ω
845Ω
CM
R3
, should be of a value
FIGURE 5. Differential Drive Circuit of Figure 4
RM
B can be used as
412Ω
698Ω
137Ω
499Ω
499Ω
(Continued)
R4
CM
R5, R6
2000Ω
1000Ω
2000Ω
499Ω
499Ω
should
19
The ADC clock line should be considered to be a transmis-
sion line and be series terminated at the source end to match
the source impedance with the characteristic impedance of
the clock line. It generally is not necessary to terminate the
far (ADC) end of the clock line, but if a single clock source is
driving more than one device (a condition that is generally
not recommended), far end termination may be needed. Far
end termination is a series RC with the resistor being the
same as the characteristic impedance of the clock line. The
capacitor should have a minimum value of
where t
length of the line and Z
the line. The units of t
each other. The typical board of FR-4 material has a t
about 150 ps/inch, or about 60 ps/cm.
The far end termination should be near but beyond the ADC
clock pin as seen from the clock source.
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12040 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 40% to 60%.
Take care to maintain a constant clock line impedance
throughout the length of the line. Refer to Application Note
AN-905 for information on setting characteristic impedance.
PD
is the propagation time in ns/unit length, "L" is the
PD
O
is the characteristic impedance of
and "L" should be consistent with
20046014
20046060
www.national.com
PD
of