ADC12D040CIVS National Semiconductor, ADC12D040CIVS Datasheet - Page 20

• Manufacturer Part Number: ADC12D040CIVS
• Description: DUAL 12BIT ADC, 40MSPS, SMD, 12D040
• Manufacturer: National Semiconductor

Specifications of ADC12D040CIVS

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Parallel
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.35V To 5.25V, 4.75V To 5.25V
• Sampling Rate: 40MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Applications Information
2.2 OEA, OEB
The OEA or OEB pin, when high, puts the output pins into a
high impedance state. When this pin is low the outputs are in
the active state. The ADC12D040 will continue to convert
whether this pin is high or low, but the output can not be read
while the pin is high.
Since ADC noise increases with increased output capaci-
tance at the digital output pins, do use the TRI-STATE out-
puts of the ADC12L066 to drive a bus. Rather, each output
pin should be located close to and drive a single digital input
pin. To further reduce ADC noise, a 100 Ω resistor in series
with each ADC digital output pin, located close to their re-
spective pins, should be added to the circuit.
2.3 PD
The PD pin, when high, holds the ADC12D040 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 75 mW
with a 40 MHz clock and 40mW if the clock is stopped. The
output data pins are undefined in this mode. The data in the
pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 4, 5, 6, 12, 13 and 14. These
capacitors loose their charge in the Power Down mode and
must be recharged by on-chip circuitry before conversions
can be accurate. Smaller capacitor values allow faster re-
covery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
2.4 OF
The output data format is offset binary when the OF pin is at
a logic low or 2’s complement when the OF pin is at a logic
high. While the sense of this pin may be changed "on the fly,"
doing this is not recommended as the output data could be
erroneous for a few clock cycles after this change is made.
3.0 OUTPUTS
The ADC12D040 has 24 TTL/CMOS compatible Data Out-
put pins. Valid data is present at these outputs while the OE
and PD pins are low. While the t
about output timing, a simple way to capture a valid output is
to latch the data on the falling edge of the conversion clock
(pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally,
bus capacitance beyond the specified 20 pF/pin will cause
t
output data. The result could be an apparent reduction in
dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connect-
ing buffers between the ADC outputs and any other circuitry
(74ACQ541, for example). Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of 100Ω at the digital outputs, close to the ADC
pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could oth-
erwise result in performance degradation. See Figure 4.
OD
to increase, making it difficult to properly latch the ADC
DR
and DR GND. These large charging current
OD
time provides information
(Continued)
20
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12D040 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
mV
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be espe-
cially careful of this during turn on and turn off of power.
The V
be operated from a supply in the range of 2.35V to V
(nominal 5V). This can simplify interfacing to low voltage
devices and systems. Note, however, that t
reduced V
higher than V
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12D040
between these areas, is required to achieve specified per-
formance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close prox-
imity to any of the ADC12D040’s other ground pins.
Capacitive coupling between the typically noisy digital cir-
cuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have sig-
nificant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients dur-
ing clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 100Ω resis-
tors in series with each data output line. Locate these resis-
tors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
P-P
DR
.
pin provides power for the output drivers and may
DR
. DO NOT operate the V
D
.
DR
OD
pin at a voltage
increases with
D