ADC12D040CIVS National Semiconductor, ADC12D040CIVS Datasheet - Page 22

• Manufacturer Part Number: ADC12D040CIVS
• Description: DUAL 12BIT ADC, 40MSPS, SMD, 12D040
• Manufacturer: National Semiconductor

Specifications of ADC12D040CIVS

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Parallel
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.35V To 5.25V, 4.75V To 5.25V
• Sampling Rate: 40MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Applications Information
FIGURE 7. Isolating the ADC Clock from other Circuitry
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12D040 with
a device that is powered from supplies outside the range of
the ADC12D040 supply. Such practice may lead to conver-
sion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
rent spikes can couple into the analog circuitry, degrading
DR
and DR GND. These large charging cur-
with a Clock Tree
(Continued)
20046017
22
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 20 pF/pin
will cause t
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12D040, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 47Ω to 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in Figure 5) will
improve performance. The LMH6702 and the LMH6628
have been successfully used to drive the analog inputs of the
ADC12D040.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting con-
figuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the speci-
fied range. As mentioned in Section 1.2, V
the range of
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
OD
to increase, making it difficult to properly latch
1.0V ≤ V
REF
≤ 2.4V
REF
o
should be in
out of phase