ADC12D040CIVS National Semiconductor, ADC12D040CIVS Datasheet - Page 4

• Manufacturer Part Number: ADC12D040CIVS
• Description: DUAL 12BIT ADC, 40MSPS, SMD, 12D040
• Manufacturer: National Semiconductor

Specifications of ADC12D040CIVS

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Parallel
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.35V To 5.25V, 4.75V To 5.25V
• Sampling Rate: 40MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ANALOG I/O
DIGITAL I/O
Pin Descriptions and Equivalent Circuits
Pin No.
15
16
11
13
14
12
60
22
41
59
21
2
1
7
5
4
6
INT/EXT REF
Symbol
V
V
V
V
V
V
V
V
V
V
V
OEA
OEB
CLK
IN
IN
IN
IN
PD
OF
RM
RM
RP
RP
RN
RN
REF
A+
B+
A−
B−
A
B
A
B
A
B
Equivalent Circuit
4
Non-Inverting analog signal Inputs. With a 2.0V reference the
full-scale input signal level is 2.0 V
pair, centered on a common V
Inverting analog signal Input. With a 2.0V reference the
full-scale input signal level is 2.0 V
pair, centered on a common V
connected to a common V
a differential input signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor when external reference is
used. V
2.4V.
V
reference is selected. With a logic high on this pin an external
reference voltage must be applied to V
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT LOAD these pins.
Digital clock input. The range of frequencies for this input is
100 kHz to 55 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
OEA and OEB are the output enable pins that, when low,
enables their respective TRI-STATE
either of these pins is high, the corresponding outputs are in a
high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
Output Format pin. A logic low on this pin causes output data
to be in offset binary format. A logic high on this pin causes
the output data to be in 2’s complement format.
REF
select pin. With a logic low at this pin the internal 2.0V
REF
is 2.0V nominal and should be between 1.0V to
Description
CM
for single-ended operation, but
CM
CM
.
. These (-) input pins may be
P-P
P-P
®
data output pins. When
on each pin of the input
on each pin of the input
REF
input pin 7.