ADC12D040CIVS National Semiconductor, ADC12D040CIVS Datasheet - Page 21
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ADC12D040CIVS
Manufacturer Part Number
ADC12D040CIVS
Description
DUAL 12BIT ADC, 40MSPS, SMD, 12D040
Manufacturer
National Semiconductor
Datasheet
1.ADC12D040CIVS.pdf
(23 pages)
Specifications of ADC12D040CIVS
Resolution (bits)
12bit
Input Channel Type
Differential
Data Interface
Parallel
Supply Voltage Range - Analogue
4.75V To 5.25V
Supply Voltage Range - Digital
2.35V To 5.25V, 4.75V To 5.25V
Sampling Rate
40MSPS
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Applications Information
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected be-
tween the converter’s input pins and ground or to the refer-
ence input pin and ground should be connected to a very
clean point in the analog ground plane.
Figure 6 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. The ADC12DL066 should be between these two
areas. Furthermore, all components in the reference circuitry
and the input signal chain that are connected to ground
should be connected together with short traces and enter the
analog ground plane at a single, quiet point. All ground
connections should have a low inductance path to ground.
FIGURE 6. Example of a Suitable Layout
(Continued)
21
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 7.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
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