IS42S16400F-7TLI INTEGRATED SILICON SOLUTION (ISSI), IS42S16400F-7TLI Datasheet - Page 12

• Manufacturer Part Number: IS42S16400F-7TLI
• Description: SDRAM, IND, 4M X 16, 3V, 54TSOP2
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S16400F-7TLI

• Access Time: 5.4ns
• Page Size: 64Mbit
• Memory Case Style: TSOP-2
• No. Of Pins: 54
• Operating Temperature Range: -40°C To +85°C
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (1M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16400F
IS45S16400F
12
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will inter-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will inter-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
9. Burst in bank n continues as initiated.
rupted by bank m’s burst.
the READ on bank n, CAS latency later (Consecutive READ Bursts).
rupt the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to
prevent bus contention.
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE
to bank n will be data-in registered one clock prior to the READ to bank m.
rupt the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP
1).
the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention.
The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin
after t
tered one clock prior to the READ to bank m (Fig CAP 3).
the WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m
(Fig CAP 4).
WR
is met, where t
wr
begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
Integrated Silicon Solution, Inc. — www.issi.com
wr
is met, where t WR begins when the
07/28/2010
Rev. H