IS42S16400F-7TLI INTEGRATED SILICON SOLUTION (ISSI), IS42S16400F-7TLI Datasheet - Page 23

• Manufacturer Part Number: IS42S16400F-7TLI
• Description: SDRAM, IND, 4M X 16, 3V, 54TSOP2
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S16400F-7TLI

• Access Time: 5.4ns
• Page Size: 64Mbit
• Memory Case Style: TSOP-2
• No. Of Pins: 54
• Operating Temperature Range: -40°C To +85°C
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (1M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16400F
IS45S16400F
diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until t
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the PRE-
CHARGE command is that it requires that the command
and address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length
or full-page bursts.
CAS Latency
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
07/28/2010
rp
is met. Note that part of the row precharge time is
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency - 2
NOP
NOP
CAS Latency - 3
T1
T1
t
LZ
t
AC
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated.The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
NOP
NOP
T2
T2
D
OUT
t
t
OH
LZ
t
AC
NOP
T3
T3
D
DON'T CARE
UNDEFINED
OUT
t
OH
T4
23