ST62T15CM6 STMicroelectronics, ST62T15CM6 Datasheet - Page 27

• Manufacturer Part Number: ST62T15CM6
• Description: 8BIT MCU OTP 2K, SMD, 62T15, SOIC20
• Manufacturer: STMicroelectronics

Specifications of ST62T15CM6

• Controller Family/series: ST6
• Core Size: 8bit
• No. Of I/o's: 20
• Program Memory Size: 2KB
• Ram Memory Size: 64Byte
• Cpu Speed: 8MHz
• Oscillator Type: External Only
• No. Of Timers: 1
• Digital Ic Case: RoHS Compliant
• Peripherals: ADC,
• Rohs Compliant: No
• Processor Series: ST62T1x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Data Ram Size: 64 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-28
• Development Tools By Supplier: ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: In Transition

6 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Each source is associated with a specific Interrupt
Vector, located in Program space (see
Mapping
table). In the vector location, the user
Figure
18.
Interrupt
must write a Jump instruction to the associated in-
terrupt service routine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Interrupts are triggered by events either on exter-
nal pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
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