ST62T15CM6 STMicroelectronics, ST62T15CM6 Datasheet - Page 45

8BIT MCU OTP 2K, SMD, 62T15, SOIC20

ST62T15CM6

Manufacturer Part Number
ST62T15CM6
Description
8BIT MCU OTP 2K, SMD, 62T15, SOIC20
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST62T15CM6

Controller Family/series
ST6
Core Size
8bit
No. Of I/o's
20
Program Memory Size
2KB
Ram Memory Size
64Byte
Cpu Speed
8MHz
Oscillator Type
External Only
No. Of Timers
1
Digital Ic Case
RoHS Compliant
Peripherals
ADC,
Rohs Compliant
No
Processor Series
ST62T1x
Core
ST6
Data Bus Width
8 bit
Program Memory Type
EPROM
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
20
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOP-28
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
In Transition

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0
WATCHDOG TIMER (Cont’d)
These instructions test the C bit and reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
For more information on the use of the watchdog,
please read application note AN1015.
9.1.5 Low Power Modes
9.1.6 Interrupts
None.
Mode
WAIT
STOP
Description
No effect on Watchdog.
Behaviour depends on the EXTCNTL option in the Option bytes:
1. Watchdog disabled:
The MCU will enter Stop mode if a STOP instruction is executed.
2. Watchdog enabled and EXTCNTL option disabled:
If a STOP instruction is encountered, it is interpreted as a WAIT.
3. Watchdog and EXTCNTL option enabled:
If a STOP instruction is encountered when the NMI pin is low, it is interpreted as a WAIT. If, however, the
STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU en-
ters STOP mode.
When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.
Note: This note applies only when the watchdog is
used as a standard timer. It is recommended to
read the counter twice, as it may sometimes return
an invalid value if the read is performed while the
counter is decremented (counter bits in transient
state). To validate the return value, both values
read must be equal. The counter decrements eve-
ry 384 µs at 8 MHz f
OSC
.
ST6215C/ST6225C
45/105
1

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