ST62T15CM6 STMicroelectronics, ST62T15CM6 Datasheet - Page 32

• Manufacturer Part Number: ST62T15CM6
• Description: 8BIT MCU OTP 2K, SMD, 62T15, SOIC20
• Manufacturer: STMicroelectronics

Specifications of ST62T15CM6

• Controller Family/series: ST6
• Core Size: 8bit
• No. Of I/o's: 20
• Program Memory Size: 2KB
• Ram Memory Size: 64Byte
• Cpu Speed: 8MHz
• Oscillator Type: External Only
• No. Of Timers: 1
• Digital Ic Case: RoHS Compliant
• Peripherals: ADC,
• Rohs Compliant: No
• Processor Series: ST62T1x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Data Ram Size: 64 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-28
• Development Tools By Supplier: ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: In Transition

ST6215C/ST6225C
6.7 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00h
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
Bit 6 = LES Level/Edge Selection bit .
0: Falling edge sensitive mode is selected for inter-
Table 7. Interrupt Mapping
32/105
1
rupt vector #1
Vector #0
Vector #1
Vector #2
Vector #3
Vector #4
7
-
number
Vector
LES
Port A
Port B, C
TIMER
ESB
RESET
NMI
ADC
Source
Block
GEN
Reset
Non Maskable Interrupt
Ext. Interrupt Port A
Ext. Interrupt Port B, C
Timer underflow
End Of Conversion
-
Description
-
NOT USED
-
0
-
Register
TSCR
ADCR
Label
N/A
N/A
N/A
N/A
1: Low level sensitive mode is selected for inter-
Bit 5 = ESB Edge Selection bit .
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
Bit 4 = GEN Global Enable Interrupt .
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bits 3:0 = Reserved, must be cleared.
rupt vector #1
EOC
Flag
TMZ
N/A
N/A
N/A
N/A
STOP
from
Exit
yes
yes
yes
yes
yes
no
FFCh-FFDh
FFEh-FFFh
FFAh-FFBh
FF8h-FF9h
FF2h-FF3h
FF6h-FF7h
FF4h-FF5h
FF0h-FF1h
Address
Vector
Priority
Highest
Priority
Lowest
Priority
Order