DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 23

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.0 Functional Description
3.10.3 Digital Adaptive Equalization
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the
frequency content of the transmitted signal can vary greatly
during
randomness of the scrambled data stream. This variation
in signal attenuation caused by frequency variations must
be compensated for to ensure the integrity of the
transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt
to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths
for
compensation which will over-compensate for shorter, less
attenuating lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization must
be adaptive to ensure proper conditioning of the received
signal independent of the cable length.
The DP83816 utilizes an extremely robust equalization
scheme
Equalization’. Traditional designs use a pseudo adaptive
equalization scheme that determines the approximate
cable length by monitoring signal attenuation at certain
frequencies. This attenuation value was compared to the
internal receive input reference voltage. This comparison
would indicate the amount of equalization to use. Although
this scheme is used successfully on the DP83223V twister,
a
normal
given
referred
operation
implementation,
to
herein
based
as
Figure 3-9 100BASE-TX BLW Event Diagram
requires
(Continued)
primarily
‘Digital
significant
Adaptive
on
the
23
it is sensitive to transformer mismatch, resistor variation
and process induced offset. The DP83223V also required
an external attenuation network to help match the incoming
signal amplitude to the internal reference.
The
Interference) from the receive data stream by continuously
adapting to provide a filter with the inverse frequency
response of the channel. When used in conjunction with a
gain stage, this enables the receive 'eye pattern' to be
opened sufficiently to allow very reliable data recovery.
Traditionally 'adaptive' equalizers selected 1 of N filters in
an attempt to match the cables characteristics. This
approach will typically leave holes at certain cable lengths,
where the performance of the equalizer is not optimized.
The DP83816 equalizer is truly adaptive.
The curves given in Figure 3-10 illustrate attenuation at
certain frequencies for given cable lengths. This is derived
from the worst case frequency vs. attenuation figures as
specified in the EIA/TIA Bulletin TSB-36. These curves
indicate the significant variations in signal attenuation that
must be compensated for by the receive adaptive
equalization circuit.
Figure 3-11 represents a scrambled IDLE transmitted over
zero meters of cable as measured at the AII (Active Input
Interface) of the receiver. Figure 3-12 and Figure 3-13
represent the signal degradation over 50 and 100 meters
of category V cable respectively, also measured at the AII.
These plots show the extreme degradation of signal
integrity and indicate the requirement for a robust adaptive
equalizer.
Digital
Equalizer
removes
ISI
www.national.com
(Inter
Symbol