DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 31

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.1.2 Configuration Command and Status Register
The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is reset whenever
the register is written, and the corresponding bit location is a 1. The lower 16-bits (15-0) are devoted to command and are
used to configure and control the device.
26-25
22-21
19-16
15-10
Bit
31
30
29
28
27
24
23
20
9
8
7
Bit Name
SERREN
DPERR
RMABT
NCPEN
SSERR
FBBEN
RTABT
STABT
DSTIM
DPD
FBB
Offset: 04h
(Continued)
Tag: CFGCS
Detected Parity Error
Refer to the description in the PCI V2.2 specification.
Signaled SERR
Refer to the description in the PCI V2.2 specification.
Received Master Abort
Refer to the description in the PCI V2.2 specification.
Received Target Abort
Refer to the description in the PCI V2.2 specification.
Sent Target Abort
Refer to the description in the PCI V2.2 specification.
DEVSELN Timing
This field will always be set to 01 indicating that DP83816 supports “medium” DEVSELN timing.
Data Parity Detected
Refer to the description in the PCI V2.2 specification.
Fast Back-to-Back Capable
DP83816 will set this bit to 1.
unused
(reads return 0)
New Capabilities Enable
When set, this bit indicates that the Capabilities Pointer contains a valid value and new capabilities such
as power management are supported. When clear, new capabilities (CAPPTR, PMCAP, PMCS) are
disabled. This bit is loaded from a strap option, MD0 pin 132. A subsequent load of the configuration data
from the EEPROM will overwrite any pre-existing value.
Unused
(reads return 0)
Unused
(reads return 0)
Fast Back-to-Back Enable
Set to 1 by the PCI BIOS to enable the DP83816 to do Fast Back-to-Back transfers (FBB transfers as a
master is not implemented in the current revision).
SERRN Enable
When SERREN and PERRSP are set, DP83816 will generate SERRN during target cycles when an
address parity error is detected from the system. Also, when SERREN and PERRSP are set and
CFG:PESEL is reset, master cycles detecting data parity errors will generate SERRN.
Unused
(reads return 0)
Access: Read Write
Size: 32 bits
31
Description
Hard Reset: 02900000h
Soft Reset: Unchanged
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