DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 40

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.2.2 Configuration and Media Status Register
This register allows configuration of a variety of device and phy options, and provides phy status information.
26-24
23-18
15-13
Bit
31
30
29
28
27
17
16
12
11
PAUSE_ADV Pause Advertise
PINT_ACEN Phy Interrupt Auto Clear Enable
ANEG_SEL
SPEED100
Bit Name
ANEG_DN
PHY_CFG
EXT_PHY
LNKSTS
FDUP
POL
Offset: 0004h
(Continued)
Tag: CFG
Link Status
Link status of the internal phy. Asserted when link is good. RO
Speed 100 Mb/s
Speed 100 Mb/s indicator for internal phy. Asserted when speed is set or has negotiated to 100 Mb/s.
De-asserted when speed has been set or negotiated to 10 Mb/s. RO
Full Duplex
Full Duplex indicator for internal phy. Asserted when duplex mode is set or has negotiated to FULL. De-
asserted when duplex mode has been set or negotiated to HALF. RO
10 Mb/s Polarity Indication
Twisted pair polarity indicator for internal phy. Asserted when operating and 10 Mb/s and the polarity has
been detected as reversed. De-asserted when polarity is normal or phy is operating at 100 Mb/s. RO
Auto-negotiation Done
Auto-negotiation done indicator from internal phy. Asserted when auto-negotiation process has
completed or is not active. RO
unused
Phy Configuration
Miscellaneous internal phy Power-On-Reset configuration control bits.
When set to a 1, this bit allows the phy interrupt source to be automatically cleared whenever the ISR is
read. When this bit is 0, the phy interrupt source must be manually cleared via access of the phy
registers. R/W
This bit is loaded from EEPROM at power-up and is used to configure the internal phy to advertise the
capability of 802.3x pause during auto-negotiation. Setting this bit to 1 will cause the pause function to be
advertised if the phy has also been configured to advertise full duplex capability (See ANEG_SEL). R/W
Auto-negotiation Select
These bits are loaded from EEPROM at power-up and are used to define the default state of the internal
phy auto-negotiation logic. R/W These bits are encoded as follows:
External Phy Support
Act as a stand-alone MAC. When set, this bit enables the MII and disables the internal Phy (sets bit 9).
R/W
Reserved
000
010
100
110
001
011
101
111
Auto-negotiation disabled, force 10 Mb/s half duplex
Auto-negotiation disabled, force 100 Mb/s half duplex
Auto-negotiation disabled, force 10 Mb/s full duplex
Auto-negotiation disabled, force 100 Mb/s full duplex
Auto-negotiation enabled, advertise 10 Mb/s half & full duplex
Auto-negotiation enabled, advertise 10/100 Mb/s half duplex
Auto-negotiation enabled, advertise 100 Mb/s half & full duplex
Auto-negotiation enabled, advertise 10/100 Mb/s half & full duplex
Access: Read Write
Size: 32 bits
40
Description
Hard Reset: 00000000h
Soft Reset: 00000000h
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