DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 45

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.2.7 Interrupt Mask Register
This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding
interrupt. During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to
cause an interrupt. ISR bits are always set to 1, however, if the condition is present, regardless of the state of the
corresponding mask bit.
31-26
Bit
Bit
25
24
23
22
21
7
6
5
4
3
2
1
0
Bit Name
Bit Name
RXEARLY
TXRCMP
RXRCMP
RXDESC
TXDESC
RXORN
RXIDLE
RXERR
DPERR
RMABT
SSERR
RXOK
TXOK
Offset: 0014h
(Continued)
Tag: IMR
Tx Descriptor
This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS field has been
updated.
Tx Packet OK
This event is signaled after the last transmit descriptor in a successful transmission attempt has been
updated with valid status.
Rx Overrun
Set when a receive data FIFO overrun condition occurs.
Rx Idle
This event is signaled when the receive state machine enters the idle state from a running state. This will
happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a descriptor
with OWN set).
Rx Early Threshold
Indicates that the initial Rx Drain Threshold has been met by the incoming packet, and the transfer of the
number of bytes specified by the DRTH field in the RXCFG register has been completed by the receive
DMA engine. This interrupt condition will occur only once per packet.
Rx Packet Error
This event is signaled after the last receive descriptor in a failed packet reception has been updated with
valid status.
Rx Descriptor
This event is signaled after a receive descriptor with the INTR bit set in the CMDSTS field has been
updated.
Rx OK
Set by the receive state machine following the update of the last receive descriptor in a good packet.
unused
Transmit Reset Complete
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Receive Reset Complete
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Detected Parity Error
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Signaled System Error
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Received Master Abort
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Access: Read Write
Size: 32 bits
45
Description
Description
Hard Reset: 00000000h
Soft Reset: 00000000h
www.national.com