DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 62

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
Accept on Multicast or Unicast Hash
Multicast and Unicast addresses may be further qualified
by use of the receive filter hash functions. An internal 512
bit (64 byte) RAM-based hash table is used to perform
imperfect filtering of multicast or unicast packets. By
enabling either Multicast Hashing or Unicast Hashing in the
RFCR, the receive filter logic will use the 9 least significant
bits of the destination addresses’ CRC as an index into the
set HASH_TABLE = 200
crc $DA
set index = ($crc >> 3)
set bit = ($crc & 01f)
# write word address into RFCR
iow l $RFCR ($HASH_TABLE + $index)
# select bit to set/clear
if ($bit > f) set bit = ($bit - 010h)
set hash_bit = (0001 << $bit)
# read indexed word from table
ior l $RFDR
if ($SetBit) then
else
endif
iow l $RFCR ($RFEN|$MHEN|$UHEN)# enable multicast and/or unicast
set hash_word = ($rc | $hash_bit)
iow l $RFDR ($hash_word)
set hash_bit = (~$hash_bit)
set hash_word = ($rc & $hash_bit)
iow l $RFDR ($hash_word)‘
Figure 4-2 Hash Table Memory - 40h bytes addressed on word boundaries
(Continued)
Bit#
17 16 15
# compute the CRC of the destination address
# lower 5 bits select which bit in 32 bit word
# use 16 bit register interface into 32bit RAM
# address hashing
X X
X X
X X
X X
X X
byte63
byte61
byte5
byte3
byte1
62
Hash Table memory. The upper 4 bits represent the word
address and the lower 5 bits select the bit within the word.
If the corresponding bit is set, then the packet is accepted,
otherwise the packet is rejected. The hash table memory is
accessed through the RFCR and the RFDR. Refer to
Figure 4-2 for a memory map. Below is example code for
setting/clearing a bit in the hash table.
8 7
byte62
byte60
byte4
byte2
byte0
0
23E
23C
204
202
200
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