ISL5416KIZ Intersil, ISL5416KIZ Datasheet - Page 4

• Manufacturer Part Number: ISL5416KIZ
• Description: IC,Downconverter,BGA,256PIN,PLASTIC
• Manufacturer: Intersil

Specifications of ISL5416KIZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
POWER SUPPLY
INPUTS
CONTROL
Cin(16:0)
Din(16:0)
SYNCIn1
SYNCIn2
Ain(16:0)
Bin(16:0)
SYNCO
RESET
NAME
VccIO
CLKA
CLKB
CLKC
CLKD
ENIA
ENIB
ENIC
ENID
GND
Vcc
TYPE
O
-
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PULL-UP/DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
INTERNAL
PULL UP
4
Positive Power Supply Voltage (core), 1.8V ±0.09
Positive Power Supply Voltage (I/O), 3.3V ±0.165
Ground, 0V.
Parallel Data Input bus A. Sampled on the rising or falling edge (programmable) of clock when ENIA
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Parallel Data Input bus B. Sampled on the rising or falling edge (programmable) of clock when ENIB
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Parallel Data Input bus C. Sampled on the rising or falling edge (programmable) of clock when ENIC
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Parallel Data Input bus D. Sampled on the rising or falling edge (programmable) of clock when ENID
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input clock for data bus A. CLKA or CLKC may be used for Ain(16:0).
Input clock for data bus B. CLKB or CLKC may be used for Bin(16:0).
Input clock for data bus C. CLKC is also the master clock for all channels of ISL5416
Input clock for data bus D. CLKD or CLKC may be used for Din(16:0).
Global synchronization input signal 1. SYNCIn1 can update the carrier NCOs, reset decimation
counters, restart the filter, and restart the output section among other functions. For most of the
functional blocks, the response to SYNCIn1 is programmable and can be enabled or disabled.
Global synchronization input signal 2. SYNCIn2 can update the carrier NCOs, reset decimation
counters, restart the filter, and restart the output section among other functions. For most of the
functional blocks, the response to SYNCIn2 is programmable and can be enabled or disabled.
Synchronization Output Signal. The processing of multiple ISL5416 devices can be synchronized by
tying the SYNCO from one ISL5416 device (the master) to the SYNCIn of all the ISL5416 devices
(the master and slaves). An optional internal SYNCO to SYNCInX connection is provided.
Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default
values.
ISL5416
DESCRIPTION