ISL5416KIZ Intersil, ISL5416KIZ Datasheet - Page 5

• Manufacturer Part Number: ISL5416KIZ
• Description: IC,Downconverter,BGA,256PIN,PLASTIC
• Manufacturer: Intersil

Specifications of ISL5416KIZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
JTAG
OUTPUTS
Aout(15:0)
Bout(15:0)
Cout(15:0)
Dout(15:0)
Eout(15:0)
CLKO2/
INTRPT
CLKO1
NAME
TRST
TCLK
TDO
TMS
TDI
TYPE
O
O
O
O
O
O
O
O
I
I
I
I
PULL-UP/DOWN
PULL DOWN
(Continued)
INTERNAL
PULL UP
PULL UP
PULL UP
5
* X denotes A, B, C, D as appropriate
Test data out
Test data in.
Test mode select.
Test clock.
Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and
there is enough board noise, the JTAG port might get into an unexpected state and stop
communications with the part
Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section. See Table 24.
Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section.
Parallel Data Output bus C. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section.
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section.
Below is the table of the serial output bits allocation for DOUT.
A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses.
Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is
programmable.
Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second
clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt
from one or more channels for a sequenced read (FIFO-like) mode. See register GWA = 0000h, bit
13.
Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q,
SSYNCX *
SCLKX *
SD1X *
SD2X *
SER. OUTPUT A SER. OUTPUT B SER. OUTPUT C SER. OUTPUT D
ISL5416
DOUT0
DOUT1
DOUT2
DOUT3
SERIAL OUTPUT BITS ALLOCATION
DESCRIPTION
DOUT4
DOUT5
DOUT6
DOUT7
DOUT10
DOUT11
DOUT8
DOUT9
DOUT12
DOUT13
DOUT14
DOUT15