KSZ8995X Micrel Inc, KSZ8995X Datasheet

Page 1

KS8995X General Description The KS8995X is a highly integrated Layer-2 QoS (Quality of Service) switch with optimized BOM (Bill of Materials) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three differ- ...

Page 2

... Home networking expansion • Standalone 10/100 switch • Hotel/campus/MxU gateway • Enterprise VoIP gateway/phone • FTTx customer premise equipment • Media converter Ordering Information Part Number Temperature Range Package KS8995X +70 C KSZ8995X + Micrel 128-Pin PQFP 128-Pin PQFP Lead Free December 2003 ...

Page 3

KS8995X Revision History Revision Date Summary of Changes 1.08 4/01/02 Created. 1.09 5/20/02 Changed MII setting descriptions. Changed pu/pd descriptions for SMRXD2. Changed pu/pd description for forced flow control. Edited large packet sizes back in, also in “Register 4.” Added ...

Page 4

KS8995X Table of Contents System Level Applications .............................................................................................................................................................. 6 Pin Description (by Number) ........................................................................................................................................................... 8 Pin Description (by Name) ............................................................................................................................................................ 13 Pin Configuration ........................................................................................................................................................................... 18 Introduction ............................................................................................................................................................................ 19 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19 100BaseTX Transmit ............................................................................................................................................................... 19 100BaseTX ...

Page 5

KS8995X Register 8 (0x08): Global Control 6 ................................................................................................................................ 32 Register 9 (0x09): Global Control 7 ................................................................................................................................ 32 Register 10 (0x0A): Global Control 8 ............................................................................................................................. 32 Register 11 (0x0B): Global Control 9 ............................................................................................................................. 33 Port Registers .......................................................................................................................................................................... 33 Register 16 (0x10): ...

Page 6

KS8995X System Level Applications CPU WAN PHY & AFE (XDSL, CM...) M9999-120403 10/100 10/100 PHY 1 MAC 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 MAC 3 PHY 3 10/100 10/100 PHY 4 MAC 4 10/100 10/10 MAC 5 ...

Page 7

KS8995X December 2003 10/100 10/100 MAC 1 PHY 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 PHY 3 MAC 3 10/100 10/100 PHY 4 MAC 4 10/100 10/100 MAC 5 PHY 5 EEPROM I/F KS8995X Figure 3. Standalone Switch ...

Page 8

KS8995X Pin Description (by Number) Pin Number Pin Name Type 1 TEST1 2 GNDA Gnd 3 VDDAR 4 RXP1 5 RXM1 6 GNDA Gnd 7 TXM1 8 TXP1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA Gnd 13 TXM2 14 ...

Page 9

KS8995X Pin Number Pin Name Type 31 VDDAR 32 RXP5 33 RXM5 34 GNDA Gnd 35 TXM5 36 TXP5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA Gnd 41 VDDAR 42 GNDA Gnd 43 VDDAR 44 GNDA Gnd 45 NC ...

Page 10

KS8995X Pin Number Pin Name Type 63 PMRXD2 Ipd/O 64 PMRXD1 Ipd/O 65 PMRXD0 Ipd/O 66 PMRXER Ipd/O 67 PCRS Ipd/O 68 PCOL Ipd/O 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD ...

Page 11

KS8995X Pin Number Pin Name Type 86 SCONF1 87 SCONF0 88 GNDD Gnd 89 VDDC 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 92 LED5-0 Ipu/O 93 LED4-2 Ipu/O 94 LED4-1 Ipu/O 95 LED4-0 Ipu/O 96 LED3-2 Ipu/O 97 LED3-1 Ipu/O 98 ...

Page 12

KS8995X Pin Number Pin Name Type 109 Reserved 110 SCL 111 SDA 112 Reserved 113 PS1 114 PS0 115 RST_N 116 GNDD Gnd 117 VDDC 118 TESTEN 119 SCANEN 120 NC 121 X1 122 X2 123 VDDAP 124 GNDA Gnd ...

Page 13

KS8995X Pin Description (by Name) Pin Number Pin Name Type 39 FXSD4 38 FXSD5 2 GNDA Gnd 6 GNDA Gnd 12 GNDA Gnd 16 GNDA Gnd 21 GNDA Gnd 27 GNDA Gnd 30 GNDA Gnd 34 GNDA Gnd 40 GNDA ...

Page 14

KS8995X Pin Number Pin Name Type 97 LED3-1 Ipu/O 96 LED3-2 Ipu/O 95 LED4-0 Ipu/O 94 LED4-1 Ipu/O 93 LED4-2 Ipu/O 92 LED5-0 Ipu/O 91 LED5-1 Ipu/O 90 LED5-2 Ipu/O 107 MDC 108 MDIO Ipu MUX1 46 ...

Page 15

KS8995X Pin Number Pin Name Type 114 PS0 113 PS1 47 PWRDN_N 48 RESERVE/NC 109 Reserved 112 Reserved 115 RST_N 5 RXM1 11 RXM2 20 RXM3 26 RXM4 33 RXM5 4 RXP1 10 RXP2 19 RXP3 25 RXP4 32 RXP5 ...

Page 16

KS8995X Pin Number Pin Name Type 111 SDA 78 SMRXC 83 SMRXD0 Ipd/O 82 SMRXD1 Ipd/O 81 SMRXD2 Ipd/O 80 SMRXD3 Ipd/O 79 SMRXDV Ipd/O 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER 1 ...

Page 17

KS8995X Pin Number Pin Name Type 41 VDDAR 43 VDDAR 125 VDDAR 9 VDDAT 18 VDDAT 24 VDDAT 37 VDDAT 50 VDDC 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Note ...

Page 18

KS8995X Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 M9999-120403 128-Pin PQFP (PQ) 18 Micrel 65 PMRXD1 PMRXD2 ...

Page 19

KS8995X Introduction The KS8995X contains five 10/100 physical layer transceivers and five MAC (Media Access Control) units with an integrated layer 2 switch. The device runs in three modes. The first mode five-port integrated switch. The second ...

Page 20

KS8995X 100BaseFX Signal Detection The physical port runs in 100BaseFX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V.The fiber module interface should be set by a voltage divider such that FXSDx ...

Page 21

KS8995X Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995X is guaranteed to learn 1K addresses and distinguishes itself from ...

Page 22

KS8995X MAC (Media Access Controller) Operation The KS8995X strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG frame is successfully transmitted, the 96 bit time IPG is measured between the two consecutive MTXEN. If the ...

Page 23

KS8995X Broadcast Storm Protection The KS8995X has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources ...

Page 24

KS8995X PHY Mode Connection External KS8995X MAC Signal MTXEN SMTXEN MTXER SMTXER MTXD3 SMTXD[3] MTXD2 SMTXD[2] MTXD1 SMTXD[1] MTXD0 SMTXD[0] MTXC SMTXC MCOL SCOL MCRS SCRS MRXDV SMRXDV MRXER Not used MRXD3 SMRXD[3] MRXD2 SMRXD[2] MRXD1 SMRXD[1] MRXD0 SMRXD[0] MRXC ...

Page 25

KS8995X SNI Interface Operation The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for ...

Page 26

KS8995X The KS8995X can classify tagged packets using the 802.1p tag based priority. In this prioritization scheme, the user can enable the 802.1p classification on a per port basis in bit 5 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 ...

Page 27

KS8995X DiffServ Field (Binary) 000000 000001 000010 000011 000100 • • • 111011 111100 111101 111110 111111 Once classification of the packets has been determined either by port-based priority, 802.1p tag-based priority or DiffServ priority, they are placed in either ...

Page 28

KS8995X Configuration Interface The KS8995X functions as a unmanaged switch EEPROM exists, the KS8995X will operate from its default and strap- in settings. I2C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995X can perform more ...

Page 29

KS8995X Register Map Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F ...

Page 30

KS8995X Address Name Register 2 (0x02): Global Control 0 (continued) 2 Buffer share mode 1 UNH mode 0 Link change age Register 3 (0x03): Global Control 1 7 Pass all frames 6 Reserved 5 IEEE 802.3x transmit flow control disable ...

Page 31

KS8995X Address Name Register 4 (0x04): Global Control 2 7 Reserved 6 Multicast storm protection disable 5 Reserved 4 Flow control and back pressure fair mode 3 No excessive collision drop 2 Huge packet support 1 Legal maximum packet size ...

Page 32

KS8995X Address Name Register 5 (0x05): Global Control 3 (continued) 1 Reserved 0 Sniff mode select Register 6 (0x06): Global Control 4 7 Switch MII back Pressure enable 6 Switch MII half duplex mode 5 Switch MII flow control enable ...

Page 33

KS8995X Address Name Register 11 (0x0B): Global Control 9 7-2 Reserved 1 LED mode 0 Reserved Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the ...

Page 34

KS8995X Address Name 0 Priority enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control ...

Page 35

KS8995X Address Name 3 Back pressure enable 2 Transmit enable 1 Receive enable 0 Learning disable Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): ...

Page 36

KS8995X Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Port 4 Control 7 Register 87 (0x57): Port 5 Control 7 Address Name 7-4 Transmit ...

Page 37

KS8995X Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Register 75 (0x4B): Port 4 Control 11 Register 91 (0x5B): Port 5 Control 11 Address Name 7 Receive ...

Page 38

KS8995X Address Name 5 Forced duplex 4 Advertised flow control capability 3 Advertised 100BT full-duplex capability 2 Advertised 100BT half-duplex capability 1 Advertised 10BT full-duplex capability 0 Advertised 10BT half-duplex capability Register 29 (0x1D): Port 1 Control 13 Register 45 ...

Page 39

KS8995X Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Port 3 Status 0 Register 78 (0x4E): Port 4 Status 0 Register 94 (0x5E): Port 5 Status 0 Address Name 7 MDIX ...

Page 40

KS8995X Address Name Register 102 (0x66): TOS priority control register 6 7-0 DSCP[15:8] Register 103 (0x67): TOS priority control register 7 7-0 DSCP[7:0] Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the ...

Page 41

KS8995X Address Name 1 Disable transmit 0 Disable LED Register 1: MII Status 15 T4 capable 14 100 Full capable 13 100 Half capable 12 10 Full capable 11 10 Half capable 10-7 Reserved 6 Preamble suppressed 5 AN complete ...

Page 42

KS8995X Register 5: Link Partner Ability 15 Next page 14 LP ACK 13 Remote fault 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 full 7 Adv 100 half 6 Adv 10 full 5 Adv 10 half 4-0 Reserved M9999-120403 ...

Page 43

KS8995X Absolute Maximum Ratings Supply Voltage ( ............................. –0.5V to +2.4V DDAR, DDAP, DDC ( ........................................ –0.5V to +4.0V DDAT, DDIO Input Voltage (All Inputs) ............................. –0.5V to +4.0V Output Voltage (All Outputs) ....................... –0.5V ...

Page 44

KS8995X Symbol Parameter 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Output Jitters 10BaseT Receive V Squelch Threshold SQ 10BaseT Transmit (measured differentially after 1:1 transformer Peak Differential Output ...

Page 45

KS8995X Timing Diagrams Receive Timing SCL SDA Figure 11. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 12. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time ...

Page 46

KS8995X Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 M9999-120403 ts2 tcyc2 th2 Figure 13. SNI Input Timing tcyc2 ...

Page 47

KS8995X Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 15. MAC Mode MII Timing–Data Received from MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Figure 16. MAC Mode MII Timing–Data Transmitted from MII Symbol Parameter t Clock Cycle (100BaseT) CYC3 t Clock Cycle ...

Page 48

KS8995X Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 17. PHY Mode MII Timing – Data Received from MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Figure 18. PHY Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BaseT) ...

Page 49

KS8995X Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC December 2003 tsr ...

Page 50

KS8995X Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...

Page 51

KS8995X Package Information MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by ...