KSZ8995X Micrel Inc, KSZ8995X Datasheet - Page 37

• Manufacturer Part Number: KSZ8995X
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers
• Manufacturer: Micrel Inc

Specifications of KSZ8995X

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1642 - BOARD EVALUATION FOR KSZ8995XA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1041

Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.
December 2003
KS8995X
Register 27 (0x1B): Port 1 Control 11
Register 43 (0x2B): Port 2 Control 11
Register 59 (0x3B): Port 3 Control 11
Register 75 (0x4B): Port 4 Control 11
Register 91 (0x5B): Port 5 Control 11
Address
7
6
5
4
3
2
1
0
Register 28 (0x1C): Port 1 Control 12
Register 44 (0x2C): Port 2 Control 12
Register 60 (0x3C): Port 3 Control 12
Register 76 (0x4C): Port 4 Control 12
Register 92 (0x5C): Port 5 Control 12
Address
7
6
Name
Receive differential
priority rate control
Low priority receive
rate control enable
High priority receive
rate control enable
Low priority receive rate
flow control enable
High priority receive
rate flow control enable
Transmit differential
priority rate control
Low priority transmit
rate control enable
High priority transmit
rate control enable
Name
Disable auto-negotiation
Forced speed
Description
1 = If bit 6 is also ‘1’ this will enable receive rate control
for this port on low priority packets at the low priority
rate. If bit 5 is also ‘1’, this will enable receive rate
control on high priority packets at the high priority rate.
0 = receive rate control will be based on the low priority
rate for all packets on this port.
1 = enable port’s low priority receive rate control feature.
0 = disable port’s low priority receive rate control.
1 = if bit 7 is also ‘1’ this will enable the port’s high
priority receive rate control feature. If bit 7 is a ‘0’ and
bit 6 is a ‘1’, all receive packets on this port will be rate
controlled at the low priority rate.
0 = disable port’s high priority receive rate control feature.
1 = flow control may be asserted if the port’s low priority
receive rate is exceeded.
0 = flow control is not asserted if the port’s low priority
receive rate is exceeded.
1 = flow control may be asserted if the port’s high
priority receive rate is exceeded. (To use this, differential
receive rate control must be on.)
0 = flow control is not asserted if the port’s high
priority receive rate is exceeded.
1 = will do transmit rate control on both high and low
priority packets based on the rate counters defined by
the high and low priority packets respectively.
0 = will do transmit rate control on any packets
The rate counters defined in low priority will be used.
1 = enable the port’s low priority transmit rate control
feature.
0 = disable the port’s low priority transmit rate control
feature.
1 = enable the port’s high priority transmit rate control
feature.
0 = disable the port’s high priority transmit rate control
feature.
Description
1 = disable auto-negotiation, speed and duplex are
decided by bit 6 and 5 of the same register.
0 = auto-negotiation is on.
1 = forced 100BT if AN is disabled (bit 7).
0 = forced 10BT if AN is disabled (bit 7).
37
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
R/W
R/W
Default
0
0
0
0
0
0
0
0
Default
0
1
M9999-120403
Micrel