KSZ8995X Micrel Inc, KSZ8995X Datasheet - Page 40

• Manufacturer Part Number: KSZ8995X
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers
• Manufacturer: Micrel Inc

Specifications of KSZ8995X

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1642 - BOARD EVALUATION FOR KSZ8995XA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1041

KS8995X
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
MIIM Registers
The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, “0x5” for port
5. The “REGAD” supported are 0,1,2,3,4,5.
M9999-120403
Address
Register 102 (0x66): TOS priority control register 6
7-0
Register 103 (0x67): TOS priority control register 7
7-0
Register 104 (0x68): MAC address register 0
7-0
Register 105 (0x69): MAC address register 1
7-0
Register 106 (0x6A): MAC address register 2
7-0
Register 107 (0x6B): MAC address register 3
7-0
Register 108 (0x6C): MAC address register 4
7-0
Register 109 (0X6D): MAC address register 5
7-0
Address
Register 0: MII Control
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Name
DSCP[15:8]
DSCP[7:0]
MACA[47:40]
MACA[39:32]
MACA[31:24]
MACA[23:16]
MACA[15:8]
MACA[7:0]
Name
Soft reset
Loop back
Force 100
AN enable
Power down
Isolate
Restart AN
Force full-duplex
Collision test
Reserved
Reserved
Force MDI
Disable auto MDIX
Disable far end fault
Description
Description
1 = PHY soft reset
0 = normal operation
1 = loop back mode (loop back at PHY)
0 = normal operation
1 = 100Mbps
0 = 10Mbps
1 = auto-negotiation enabled
0 = auto-negotiation disabled
1 = power down
0 = normal operation
NOT SUPPORTED
1 = restart auto-negotiation
0 = normal operation
1 = full-duplex
0 = half-duplex
NOT SUPPORTED
1 = force MDI
0 = normal operation
1 = disable auto MDIX
0 = normal operation
1 = disable far end fault detection
0 = normal operation
40
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
RO
R/W
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
RO
R/W
R/W
R/W
Default
00000000
00000000
0x00
0x10
0xA1
0xff
0xff
0xff
Default
0
0
1
1
0
0
0
0
0
0
0
0
0
0
December 2003
Micrel