KSZ8995X Micrel Inc, KSZ8995X Datasheet - Page 35

• Manufacturer Part Number: KSZ8995X
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers
• Manufacturer: Micrel Inc

Specifications of KSZ8995X

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1642 - BOARD EVALUATION FOR KSZ8995XA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1041

Note:
Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for
egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
December 2003
KS8995X
Address
3
2
1
0
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Register 67 (0x43): Port 4 Control 3
Register 83 (0x53): Port 5 Control 3
Address
7-0
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Register 68 (0x44): Port 4 Control 4
Register 84 (0x54): Port 5 Control 4
Address
7-0
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
Register 69 (0x45): Port 4 Control 5
Register 85 (0x55): Port 5 Control 5
Address
7-0
Register 22 (0x16): Port 1 Control 6
Register 38 (0x26): Port 2 Control 6
Register 54 (0x36): Port 3 Control 6
Register 70 (0x46): Port 4 Control 6
Register 86 (0x56): Port 5 Control 6
Address
7-0
Name
Back pressure enable
Transmit enable
Receive enable
Learning disable
Name
Default tag [15:8]
Name
Default tag [7:0]
Name
Transmit high priority
rate control [7:0]
Name
Transmit low priority
rate control [7:0]
Description
1 = enable port’s half-duplex back pressure.
0 = disable port’s half-duplex back pressure.
1 = enable packet transmission on the port.
0 = disable packet transmission on the port.
1 = enable packet reception on the port.
0 = disable packet reception on the port.
1 = disable switch address learning capability.
0 = enable switch address learning.
Description
Port’s default tag, containing
7-5: user priority bits
4: CFI bit
3-0 : VID[11:8]
Description
Default port 1’s tag, containing
7-0: VID[7:0]
Description
This along with port control 7, bits [3:0] form a 12-bit
field to determine how many “32Kbps” high priority
blocks can be transmitted. (In a unit of 4K bytes in a
one second period.)
Description
This along with port control 7, bits [7:4] form a 12-bit
field to determine how many “32Kbps” low priority
blocks can be transmitted. (In a unit of 4K bytes in a
one second period.)
35
Mode
R/W
R/W
R/W
R/W
Mode
R/W
Mode
R/W
Mode
R/W
Mode
R/W
Default
Pin PMRXD2 strap
option. Pull-down (0):
disable back
pressure. Pull-up(1):
enable back
pressure.
Note: PMRXD2 has
internal pull-down.
1
1
0
Default
0
Default
1
Default
0
Default
0
M9999-120403
Micrel