KSZ8995X Micrel Inc, KSZ8995X Datasheet - Page 28

• Manufacturer Part Number: KSZ8995X
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers
• Manufacturer: Micrel Inc

Specifications of KSZ8995X

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1642 - BOARD EVALUATION FOR KSZ8995XA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1041

KS8995X
Configuration Interface
The KS8995X functions as a unmanaged switch. If no EEPROM exists, the KS8995X will operate from its default and strap-
in settings.
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, the KS8995X can perform more advanced features like broadcast storm protection and rate control.
The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the memory map, except
the status registers. The configuration access time (t
To configure the KS8995X with a pre-configured EEPROM use the following steps:
Note: For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset operation.
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995X. An external device with MDC/MDIO capability
is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard please reference the IEEE
802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the
KS8995X. It can only access the standard MII registers. See “MIIM Registers” section.
M9999-120403
• At the board level, connect pin 110 on the KS8995X to the SCL pin on the EEPROM. Connect pin 111 on the
• Be sure the board level reset signal is connected to the KS8995X reset signal on pin 115 (RST_N).
• Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that
• Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KS8995X to the SDA pin on the EEPROM.
the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other data
will be ignored.
KS8995X. After the reset is deasserted, the KS8995X will begin reading configuration data from the EEPROM. The
configuration access time (t
RST_N
SCL
SDA
Figure 10. EEPROM Configuration Timing Diagram
prgm
) is less than 15ms.
prgm
) is less than 15ms as shown in Figure 10.
28
t prgm <15 ms
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December 2003
Micrel