LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 18

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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13.0 Inputs/Outputs
of these issues caused problems that were difficult to work
around so moving to monitoring the fuse was selected as the
solution.
These inputs do not have to be used for monitoring SCSI
fuses. Assertion of the SCSI_TERMx inputs to a Low sets
the associated bits the status registers. Therefore, any active
low signal could be connected to these pins to generate an
error event.
13.5 VRD1_HOT AND VRD2_HOT INPUTS
These inputs monitor the thermal sensor associated with
each processor VRD on a baseboard. When one of the
inputs is activated, it indicates that the VRD has exceeded a
predetermined temperature threshold. The LM93 responds
by gradually increasing the duty cycle of any PWM outputs
that are bound to the corresponding processor and setting
the appropriate error status bits. The corresponding
PROCHOT signal is also asserted. See the Section 15.10
FAN CONTROL and the Section 12.11 PROCHOT OUTPUT
CONTROL for more information.
13.6 GPIO PINS
The LM93 has 8 GPIO pins than can act as either as inputs
or outputs. Each can be configured and controlled indepen-
dently. When acting as an input the pin can be masked to
prevent it from setting a corresponding bit in the GPI Error
status registers.
13.7 FAN TACH INPUTS
The fan inputs are Schmitt-Trigger digital inputs. Schmitt-
trigger input circuitry is included to accommodate slow rise
and fall times typical of fan tachometer outputs.
The maximum input signal range is 0V to +6.0V, even when
V
supplied from fan outputs, which exceed 0V to +6.0V, either
resistive attenuation of the fan signal or diode clamping must
be included to keep inputs within an acceptable range,
thereby preventing damage to the LM93.
Hot plugging fans can involve spikes on the Tach signals of
up to 12V so diode protection or other circuitry is required.
For “Hot Plug” fans, external clamp diodes may be required
for signal conditioning.
14.0 SMBus Interface
The SMBus is used to communicate with the LM93. The
LM93 provides the means to monitor power supplies for fan
status and power failures. LM93 is designed to be tolerant to
5V signalling. Necessary pull-ups are located on the base-
board. Care should be taken to ensure that only one pull-up
is used for each SMBus signal. For proper operation, the
SMBus slave addresses of all devices attached to the bus
must comply with those listed in this document. The SMBus
interface obeys the SMBus 2.0 protocols and signaling lev-
els.
The SMBus interface of the LM93 does not load down the
SMBus if no power is applied to the LM93. This allows a
module containing the LM93 to be powered down and re-
placed, if necessary.
14.1 SMBUS ADDRESSING
Each time the LM93 is powered up, it latches the assigned
SMBus slave address (determined by ADDR_SEL) during
the first valid SMBus transaction in which the first five bits of
DD
is less than 5V. In the event that these inputs are
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18
the targeted slave address match those of the LM93 slave
address. Once the address has been latched, the LM93
continues to use that address for all future transactions until
power is lost.
The address select input detects three different voltage lev-
els and allows for up to 3 devices to exist in a system. The
address assignment is as follows:
14.2 DIGITAL NOISE EFFECT ON SMBUS
COMMUNICATION
Noise coupling into the digital lines (greater than 150mV),
overshoot greater than V
may prevent successful SMBus communication with the
LM93. SMBus No Acknowledge (NACK) is the most com-
mon symptom, causing unnecessary traffic on the bus. Al-
though, the SMBus maximum frequency of communication is
rather low (100 kHz max), care still needs to be taken to
ensure proper termination within a system with multiple parts
on the bus and long printed circuit board traces. The LM93
includes on chip low-pass filtering of the SMBCLK and SMB-
DAT signals to make it more noise immune. Minimize noise
coupling by keeping digital traces out of switching baseboard
areas as well as ensuring that digital lines containing high
speed data communications cross at right angles to the
SMBDAT and SMBCLK lines.
14.3 GENERAL SMBUS TIMING
The SMBus 2.0 specification defines specific conditions for
different types of read and write operations but in general the
SMBus protocol operates as follows:
The master initiates data transfer by establishing a START
condition, defined as a high to low transition on the serial
data line SMBDAT while the serial clock line SMBCLK re-
mains high. This indicates that a data stream follows. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next 8 bits. This consists of
a 7-bit slave address (MSB first) plus a R/W bit, which
determines the direction of the data transfer, i.e. whether
data is written to or read from the slave device (0 = write, 1
= read).
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the Ac-
knowledge Bit, and holding it low during the high period of
this clock pulse. All other devices on the bus now remain idle
while the selected device waits for data to be read from or
written to it. If the R/W bit is a 0 then the master writes to the
slave device. If the R/W bit is a 1 the master reads from the
slave device.
Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge bit. Data
transitions on the data line must occur during the low period
of the clock signal and remain stable during the high period,
as a low to high transition when the clock is high may be
interpreted as a STOP signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It may be an instruction, such as
Address Select Pin
(ADDR_SEL)
V
High
Low
DD
/2
DD
and undershoot less than GND,
Slave Address
Assignment
01011 01
01011 10
01011 00