LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 74

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Register
Address
16.0 Registers
16.8.18 Register CDh PWM2 Control 2
CDh
Read/
Write
R/W
7:4
Bit
0
1
2
3
Control 2
Register
PWM2
Name
(Continued)
OVR_DC
Name
EPPL
OVR
PPL
INV
Bit 7
R/W
R/W
R/W
R/W
R/W
R/W
Bit 6
OVR_DC
When set, enables manual duty cycle override for
PWM2.
Invert PWM1 output. When 0, 100% duty cycle
corresponds to the PWM output continuously HIGH.
When 1, 100% duty cycle corresponds to the PWM
output continuously LOW.
Enable PROCHOT PWM2 lock. When set, this bit
causes bound PROCHOT events on PWM2 to trigger
PPL (bit [3]). When cleared, PPL never gets set.
PROCHOT PWM2 lock. When set, this bit indicates
that PWM2 is currently being held at 100% because a
bound PROCHOT event occurred while EPPL (bit [2])
was set. This bit is cleared by writing a zero. Clearing
this bit allows the fans to return to normal operation.
This bit is not locked by the LOCK bit in the LM93
Configuration register.
This field sets the duty cycle that will be used by
PWM2 whenever manual override mode is active.
This field accepts 16 possible values that are mapped
to duty cycles according the table in the Fan Control
section. Whenever this register is read, it returns the
duty cycle that is currently being used by PWM2
regardless of whether override mode is active or not.
The value read may not match the last value written if
another control source is requesting a greater duty
cycle. This field always returns 0h when the PWM2
spin up cycle is active.
Bit 5
74
Bit 4
Description
Bit 3
PL
EPPL
Bit 2
Bit 1
INV
Bit 0
OVR
Default
Value
00h