LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 24

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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14.0 SMBus Interface
14.5.4.4 Simulated SMBus Block-Write Block-Read Process Call
Alternatively, if the master cannot support an SMBus Block-Write Block-Read process call, it can be emulated by two transactions
(a block write followed by a block read). This should only be done in a single master system, since in a dual master system
collisions can occur that corrupt the data and transaction. Below is the sequence of events for these transactions:
1. The master issues a START to start this transaction.
2. The master sends the 7-bit slave address followed by a write bit (low).
3. The slave asserts the ACK.
4. The master sends the Block Read command code (F1h) and the slave asserts the ACK.
5. The master sends the Byte Count (2h) for this transaction and the slave asserts the ACK.
6. The master sends the Start Register Address and the slave asserts the ACK.
7. The master sends the Byte Count (1-20h) for the Block-Read Process Call and the slave asserts the ACK.
8. The master sends a STOP to end this transaction.
9. The master sends a START to start this transaction.
10. The master sends the 7-bit slave address followed by a write bit (low) and the slave asserts the ACK.
11. The master sends the Block Read Command code (F1h) and the slave asserts the ACK.
12. The master sends a repeat START.
13. The master sends the 7-bit slave address followed by a read bit (high) and the slave asserts the ACK.
14. The master receives Byte Count (this matches the size sent by the master in step 7) and asserts the ACK.
15. The master receives Data Byte 1 and asserts the ACK.
16. The master receives Data Byte 2 and asserts the ACK.
17. The master receives N-3 data bytes, and asserts ACK for each one.
18. The master receives the last data byte and asserts a NACK.
19. The master issues a STOP to end this transaction.
Special Notes:
1. Steps 9 through 19 can be repeated to read another block of data. The address auto-increments such that the next block
2. The LM93 returns 00h when address locations outside of normal address space are read.
3. Block reads do not wrap around from address FFh to 00h
4. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not
5. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master
6. After a block read is finished, the base address of the LM93 is updated to point to the byte just beyond the last byte read.
14.5.4.5 SMBus Fixed Address Block Reads
Block reads can be performed from pre-defined addresses. A special command code has been reserved for each pre-defined
address. See the Section 14.5.2 Block Command Code Summary for more details on the command codes. Below is the
sequence of events that occur for this type of block read:
1. The master sends a START to start this transaction.
2. The master sends the 7-bit slave address followed by a write bit (low).
3. The slave asserts an ACK.
4. The master sends a Fixed Block Command Code (F2h-FDh) and the slave asserts an ACK.
A
1
S
starts where the last block left off. The size returned by the LM93 is the same each time.
acknowledge a byte.
to issue a STOP signal.
11
Block
Read
Command
Code
(F1h)
2
Slave
Address
A
W
12 13
S
3
A
Slave
Address
4
Block
Read
Command
Code
(F1h)
(Continued)
R
A
A
5
Byte
Count
(2h)
14
Byte
Count
(1–20h)
(N)
A
6
Start
Register
Address
24
A
15
Data
Byte 1
A
7
Byte
Count
(1–20h)
(N)
A
16
Data
Byte 2
A
8
P
A
9
S
A
10
Slave
Address
17
Data
Byte N
W
/A
A
16
P
A