LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 21

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.0 SMBus Interface
14.5.3.3 SMBus Write Block to Any Address
The start address for a block write is embedded in this transaction. In this operation the master sends a block of data to the slave
as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a command code that tells the slave device to expect a block write. The LM93 command code for a block
5. The slave asserts ACK.
6. The master sends a byte that tells the slave device how many data bytes it will send (N). The SMBus specification allows a
7. The slave asserts ACK.
8. The master sends data byte 1, the starting address of the block write.
9. The slave asserts ACK after each data byte.
10. The master sends data byte 2.
11. The slave asserts ACK.
12. The master continues to send data bytes and the slave asserts ACK for each byte.
13. The master asserts a STOP condition to end the transaction.
Special Notes
1. Any attempts to write to bytes beyond normal address space are acknowledged by the LM93 but are ignored.
2. Block writes do not wrap from address FFh back to 00h the address remains at FFh.
3. The Byte Count field is ignored by the LM93. The master device may send more or less bytes and the LM93 accepts them.
4. The SMBus specification requires that block writes never exceed 32 data bytes. Meeting this requirement means that only 31
14.5.3.4 I
In this transaction the master sends a block of data to the LM93 as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends the starting address of the block write.
5. The slave asserts ACK after each data byte.
6. The master sends data byte 1.
7. The slave asserts ACK.
8. The master continues to send data bytes and the slave asserts ACK for each byte.
9. The master asserts a STOP condition to end the transaction
Special Notes:
1. Any attempts to write to bytes beyond normal address space are acknowledged by the LM93 but are ignored.
2. Block writes do not wrap from address FFh back to 00h the address remains at FFh.
1
S
write is F0h.
maximum of 32 data bytes to be sent in a block write.
actual data bytes can be sent (the register address counts as one byte). The LM93 does not care if this requirement is met.
2
Slave
Address
2
C
™
Block Write
W
1
S
3
A
2
Slave
Address
4
Command
F0h
(Block
Write)
W
(Continued)
5
A
3
A
6
Byte
Count
(N)
4
Register
Address
7
A
5
A
21
8
Data
Byte 1
(Start
Address)
6
Data
Byte 1
9
A
7
A
10
Data
Byte 2
A
8
Data
Byte N
11
A
A
A
A
12
Data
Byte N
9
P
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A
13
P