PIC18F1230-I/SS Microchip Technology, PIC18F1230-I/SS Datasheet - Page 34

• Manufacturer Part Number: PIC18F1230-I/SS
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1230-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: USART
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 2
• Processor Series: PIC18F
• Core: PIC
• Data Ram Size: 256 B
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

PIC18F1230/1330
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
FIGURE 4-3:
FIGURE 4-4:
DS39758D-page 34
IOBST
.
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
CPU
Note 1: T
CPU Clock
Multiplexer
Peripheral
PLL Clock
Program
INTOSC
Counter
Output
OSC1
Clock
2: Clock transition typically occurs within 2-4 T
Q1
SCS1:SCS0 bits Changed
Q2
TRANSITION TIMING TO RC_RUN MODE
PC
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
OST
Q3
= 1024 T
Q4
Q1
OSC
Q1
1
; T
T
OST (1)
PLL
PC
2
= 2 ms (approx). These intervals are not shown to scale.
Q2
Clock Transition
3
T
PLL
OSTS bit Set
Q3
(1)
OSC
PC + 2
(1)
n-1
Q4
.
OSC
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
n
.
Q1
1
Transition
2
Clock
n-1 n
(2)
Q2
PC + 2
Q3
Q2
Q4
 2009 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
Q3
Q3