C40K-CDR-A Omron, C40K-CDR-A Datasheet - Page 221

• Manufacturer Part Number: C40K-CDR-A
• Description: PROGRAMMABLE CONTROLLER CPU
• Manufacturer: Omron

Specifications of C40K-CDR-A

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

END – END(01). See instruction set
END WAIT – ENDW(62). See instruction set
END(01). See instruction set
ENDW(62). See instruction set
Equal Flag. See data areas
Error Flag. See data areas
errors
Factory Intelligent Terminal. See Peripheral Devices
First Cycle Flag. See instruction set
FIT. See Peripheral Devices
flags
Floppy Disk Interface Unit. See Peripheral Devices
GPC. See Peripheral Devices
Graphic Programming Console. See Peripheral Devices
Greater Than Flag. See data areas
HDM(61). See instruction set
high–speed drum counter reset. See data areas
HIGH-SPEED DRUM COUNTER – HDM(61). See instruc-
HIGH-SPEED TIMER – TIMH(15). See instruction set
HR area. See data areas
I/O bits available
I/O REFRESH – IORF(97). See instruction set
I/O response time,
I/O Units. See Units
IL(02). See instruction set
ILC(03). See instruction set
input bit, definition of,
input devices, definition of,
input point, definition of,
216
cassette tape operations,
clearing messages,
fatal,
message tables,
non–fatal,
reading and clearing messages,
SR area flags,
execution affect,
usage,
in CPUs,
in Expansion I/O Units,
tion set
E
F–H
I
Index
input signal, definition of,
instruction set
ADD(30),
Analog Timer Unit,
AND,
AND LD,
AND NOT,
BCD(24),
BIN(23),
CLC(41),
CMP(20),
CNT,
CNTR(12),
DIFD(14)
DIFU(13)
DIV(33),
DMPX(77),
END(01), ,
ENDW(62),
HDM(61),
IL(02),
ILC(03),
IORF(97),
JME(05),
JMP(04),
KEEP(11)
LD,
LD NOT,
MLPX(76),
MOV(21),
MUL(32),
MVN(22),
NETW(63),
NOP(00),
NOT,
OR,
OR LD,
OR NOT,
OUT,
OUT NOT,
combining with OR,
use in ladder diagrams,
combining with OR LD,
use in logic blocks,
use in ladder diagrams,
changing set value,
as a bit control instruction,
use in interlocks,
as a bit control instruction,
use in interlocks,
converting to mnemonic code,
use in branching,
converting to mnemonic code,
use in branching,
as a bit control instruction,
controlling bit status,
use in ladder diagrams,
use in ladder diagrams,
combining with AND,
use in ladder diagrams,
combining with AND LD,
use in logic blocks, ,
use in ladder diagrams,
using to control bit status,
using to control bit status,