IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 107

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
2..0
3
4
5
7..6
8
10..9
Table 3–17. Status Register Format (Part 1 of 2)
Data
Bit
Unused
int_stat
cap_list_ena
pci_66mhz_capable
Unused
dat_par_rep
devsel_tim
Mnemonic
Status Register
Status is a 16-bit register that provides the status of bus-related events.
Read transactions from the status register behave normally. However,
status register write transactions are different from typical write
transactions because bits in the status register can be cleared but not set.
A bit in the status register is cleared by writing a logic one to that bit. For
example, writing the value 0x4000 to the status register clears bit 14 and
leaves the rest of the bits unchanged. The default value of the status
register is 0x0400. Refer to
Read/Write
–
Read
Read
Read
–
Read/write
Read
PCI Compiler Version 10.1
Reserved.
Interrupt status. This bit is read only and is set when the
int_dis
intan
the local side on the
Capabilities list enable. This bit is read only and is set by the
user when enabling the Capabilities List Pointer through
the wizard. When set, this bit enables the capabilities list
pointer register at offset 0x34. Refer to
on page 3–42
PCI 66-MHz capable. When set,
indicates that the PCI device is capable of running at 66
MHz. The PCI MegaCore functions can function at either 66
MHz or 33 MHz depending on the device used. You can set
this bit to
page of the IP Toolbench Parameterize - PCI Compiler
wizard.
Reserved.
Reported data parity. When high,
that during a read transaction the function asserted the
perrn
transaction the
device. This bit is high only when the
the command register) is also high. This signal is driven to
the local side on the
Device select timing. The
access timing of the function via the
PCI MegaCore functions are designed to be slow target
devices (i.e.,
is asserted on the PCI bus. This signal is driven to
output as a master device, or that during a write
Table
1
bit (bit 10 of the command register) is 0 and
by turning on PCI 66MHz Capable on the initial
devsel_tim = B"10
for more details.
3–17.
perrn
stat_reg[6]
stat_reg[0]
output was asserted as a target
Definition
devsel_tim
pci_66mhz_capable
dat_par_rep
Functional Description
devseln
perr_ena
output.
output.
").
“Capabilities Pointer”
bits indicate target
output. The
bit (bit 6 of
indicates
3–33