IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 297

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Table 7–9. Translation of Avalon Requests to PCI Requests (Part 1 of 2)
Width
Data
Path
64
64
32
32
32
64
64
Avalon
Count
Burst
>1
>1
1
1
1
1
1
Read or
write
Read
Write
Read and
write
Read and
write
Read
Write
Operation
Type of
1
There are several factors that control how Avalon-MM transactions
(bursts or single cycle) are translated to PCI transactions. These cases are
discussed in
place for situations where 32-bit Avalon-MM masters (for example, the
Nios
bridge.
®
II processor) talk to 32-bit PCI targets through a 64-bit PCI-Avalon
Any value
Any value
Any value
Upper 4 bytes
disabled; lower 4
bytes any value
Upper 4 bytes any
value; lower 4 bytes
disabled
Bytes enabled in both
the upper and lower
DWORD
Bytes enabled in both
the upper and lower
DWORD
Avalon Byte Enables
Avalon-MM burst read requests are treated as if they are going
to prefetchable PCI space. Therefore, if the PCI target space is
non-prefetchable, you should not use read bursts.
PCI Compiler Version 10.1
Table
7–9. Remember that some optimizations are put in
Single data phase read or write, PCI byte enables
identical to Avalon byte enables
Attempt to burst on PCI. All data phases will have
all PCI bytes enabled.
Attempt to burst on PCI. All data phases will have
PCI byte enables identical to the Avalon byte
enables.
Only a single 32-bit data phase (
asserted) with the lower 4 byte enables sent to
PCI, and lower 32 bits of data if a write.
Only a single 32-bit data phase (
asserted) to the odd
enables sent to PCI (and upper 32 bits of data if a
write).
A single 64-bit data phase is attempted (
asserted) with the Avalon byte enables sent to PCI.
If the target does not assert ack64n and
disconnects after a single data phase, the
transaction is resumed as a single cycle 32-bit
request (
enables will be the upper 4 byte enables from the
original Avalon request.
A 32-bit two data phase burst is attempted
(
byte enables from Avalon sent in consecutive PCI
data phases.
If the target disconnects after the first data phase,
the request will be resumed as a 32-bit single data
phase transfer.
req64n
Resulting PCI Operation and Byte Enables
req64n
not asserted) with the lower and upper
not asserted). The PCI byte
DWORD
Functional Description
with the upper 4 byte
req64n
req64n
req64n
not
not
7–29