IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 228

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Local Reference Design
4–18
PCI Compiler User Guide
The dma_bc_la register location includes the following 3 fields:
■
■
■
1
Figure 4–4
Figure 4–4. dma_bc_la Fields
Table 4–11
bits are reserved for the transaction control field, only 4 bits are used:
To initiate PCI transactions with Altera PCI MegaCore as a master, you
must perform a 32-bit single-cycle write transaction to the dma_sa
register followed by a 32-bit single-cycle write transaction to the
dma_bc_la register. The write to the dma_bc_la register triggers the
master control unit, which requests a master transaction and executes it
as indicated in the transaction control part of the dma_bc_la register.
0000
0010
0100
0110
1000
1010
Table 4–11. Transaction Control Field
Local address—starting address at which the transaction begins
reading or writing data during a PCI transaction.
Byte count—number of DWORDs transferred during a PCI transaction
Transaction control—type of transaction to be initiated
Transaction Control (Binary)
The byte count field is only used for memory transactions. For
I/O transactions this value is ignored. Because I/O transactions
are always 1 DWORD long, the data is transferred to the 32-bit I/O
register.
PCI Compiler Version 10.1
shows definition of the transaction control field. Although 8
shows the mapping of the dma_bc_la fields.
Bit
31...........28 27...........16 15............8 7...............0
Transaction
Control
Reserved
32-Bit Memory Read
64-Bit Memory Read
32-Bit I/O Read
32-Bit I/O Write
32-Bit Memory Write
64-Bit Memory Write
Byte Count
Initiated Transaction Type
Address
Local
Altera Corporation
January 2011