IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 300

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Master Operation
7–32
PCI Compiler User Guide
Burst count satisfied
Latency timer expiring during configuration, I/O, or
memory write command
Avalon-to-PCI command/write data buffer running out
of data
PCI target disconnect
PCI target retry
PCI target-abort
PCI master-abort
Table 7–10. PCI Master Write Request Termination Conditions
Termination condition
The PCI-Avalon bridge will not combine multiple Avalon-MM writes to
consecutive locations into a single PCI write transaction. No attempt is
made to byte merge separate Avalon-MM writes that write to separate
bytes in the same DWORD or QWORD into a single PCI write operation.
The PCI interface will attempt to burst as long as it can. A PCI write burst
can be terminated for various reasons.
action for the PCI master write request termination condition.
Avalon-to-PCI Read Requests
For read requests from the interconnect, the request is pushed on the PCI
bus by a configuration read, I/O read, memory read, memory read line,
or memory read multiple command. The PCI read is issued to
configuration, I/O, or memory space based on the address translation
table entry. Refer to
If a memory space read request can be completed in a single data phase,
it is issued as a memory read command. If the memory space read request
spans more than one data phase but does not cross a cacheline boundary
(as defined by the cacheline size register), it is issued as a memory read
line command. If the memory space read request crosses a cache line
boundary, it is issued as a memory read multiple command.
PCI Compiler Version 10.1
“Avalon-to-PCI Address Translation” on page
Normal master-initiated termination on PCI bus,
command completes, and the master controller
proceeds to the next command.
Normal master-initiated termination on PCI bus, the
continuation of the PCI write is requested from the
master controller arbiter.
Normal master-initiated termination on the PCI bus.
Master controller waits for the buffer to reach 8
DWORD
or there is enough data to complete the remaining burst
count. Once enough data is available, the continuation
of the PCI write is requested from the master controller
arbiter.
The continuation of the PCI write is requested from the
master controller arbiter.
The PCI interrupt status register bit,
ERR_PCI_WRITE_FAILURE (bit 0), is set to 1. The rest
of the write data is read from the buffer and discarded.
s on a 32-bit PCI or 16
Table 7–10
Resulting Action
describes the resulting
DWORD
Altera Corporation
s on a 64-bit PCI,
January 2011
7–35.