IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 173

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–32. 32-Bit PCI & 32-Bit Local-Side Master Burst Memory Read Transaction
Note to
(1)
Altera Corporation
January 2011
This signal is not applicable to the pci_mt32 MegaCore function.
(1) l_cbeni[7..4]
Figure
l_dato[63..32]
lm_adr_ackn
l_dato[31..0]
l_cbeni[3..0]
l_hdat_ackn
l_ldat_ackn
l_adi[31..0]
lm_tsr[9..0]
lm_req32n
ad[63..32]
cben[3..0]
cben[7..4]
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
Êack64n
framen
req64n
par64
stopn
irdyn
trdyn
reqn
gntn
par
clk
3–32:
1
000
2
Figure 3–32
side master interface requests a 32-bit transaction by asserting
lm_req32n. This figure applies to both pci_mt64 and pci_mt32,
excluding the 64-bit extension signals as noted for pci_mt32. The
pci_mt64 function does not assert req64n on the PCI side. Therefore,
the upper address ad[63..32] and the upper command/byte enables
cben[7..4] are invalid.
3
001
4
PCI Compiler Version 10.1
shows the same transaction as in
5
002
Adr
0
0
6
6
Adr
004
BE_L
6
7
Adr-PAR
Z
8
008
D0_L
Z
BE_L
9
D0-L-PAR
D1_L
D0_L
10
D1-L-PAR
Figure
D2_L
D1_L
108
11
Functional Description
D2-L-PAR
D2_L
3–31, but the local
12
Z
Z
000
13
3–99