IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 46

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

The Quartus II Simulation Files
The Quartus II
Simulation Files
1–12
PCI Compiler User Guide
6.
7.
8.
This section contains information about the Quartus II simulation files
supplied with the pci_mt64, pci_mt32, pci_t64, and pci_t32
MegaCore functions. These simulation files are provided in .vwf format.
You can use these simulation files to further understand the local-side
behavior of the PCI MegaCore functions for different PCI bus conditions.
In addition, you can modify the simulation files to simulate the scenarios
of interest.
The simulation files are based on the parameter settings used in pci_top.v.
There is a separate pci_top.v file for each of the four MegaCore functions.
The files are located in <path>\pci_compiler\
megawizard_flow\qexamples\<PCI MegaCore function>. This example
design file implements 6 base address registers (BARs), and an expansion
ROM BAR, with the following attributes:
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The simulation files contain functional simulation waveforms and should
be used after choosing Generate Functional Simulation Netlist
(Processing menu) for your design.
For more information regarding simulating with .vwf files, refer to
“Simulation in the Quartus II Software” on page
The following sections describe the simulation files provided with the
PCI Compiler.
In the Simulation input, specify <path>\pci_compiler\
megawizard_flow\qexamples\pci_mt64\sim\target\
cfg_wr_rd.vwf.
Click Start to start the simulation.
Click Report to view the simulation results.
BAR0 reserving 256 Megabytes (MBytes) (memory)
BAR1 reserving 64 Bytes (I/O)
BAR2 reserving 16 MBytes (memory)
BAR3 reserving 1 MByte (memory)
BAR4 reserving 64 Kilobytes (KBytes) (memory)
BAR5 reserving 4 KBytes (memory)
Expansion ROM BAR reserving 1 MByte (memory)
PCI Compiler Version 10.1
1–11.
Altera Corporation
January 2011