IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 135
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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External PHYs
Figure 4–1. 16-bit SDR Mode
Altera Corporation
December 2006
External connection in user logic
clk125_out
clk125_in
refclk
16-bit SDR Mode with a Source Synchronous TxClk
The implementation of the 16-bit SDR mode with a source synchronous
TxClk is shown in
<variation name>.v or <variation name>.vhd. In this mode the following
clocking scheme is used:
■
■
■
refclk is used as the clk125_in for the core
refclk clocks a single data rate register for the incoming receive
data
refclk clocks the Transmit Data Register (txdata) directly
rxdata
txdata
PCI Express Compiler Version 6.1
Mode 1
Q
Q
Q 4
Q
PLL
A
D
1
1
4
125Mhz SDR Mode without txclk
Figure 4–2
ENB
ENB
ENB
Q 1
Q 4
D
D
A
A
clk125_early
and is included in the file
A
D
ENB
tlp_clk_62p5
Q 1
Q 4
PCI Express Compiler User Guide
PCIe IP MegaCore
clk125_in
tlp_clk
refclk
clk125_out
4–3
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