IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 233
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 233 of 256
- Download datasheet (2Mb)
Altera Corporation
December 2006
rx_reqid_tlp
rx_ok_tlp
tx_req_tlp
tx_ack_tlp
tx_dreq_tlp
tx_err_tlp
gnt_vc
tx_ok_tlp
lpm_sm
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 2 of 17)
Signal
TRN rxtl
TRN rxtl
TRN txtl
TRN txtl
TRN txtl
TRN txtl
TRN txtl
TRN txtl
CFG pmgt 55:52
Subblock
37:14
38
39
40
41
42
50:43
51
PCI Express Compiler Version 6.1
Bit
Receive ReqID
of the completion transaction layer packet when
rx_hval_tlp
The 8 MSBs of this signal also report the type and format of the
transaction when
Receive sequencing valid. This is a sequencing signal pulse. All
previously-described signals (
only when this signal is asserted.
Transmit request to data link layer. This signal is a global virtual
channel request for transmitting transaction layer packet to the
data link layer.
Transmit request acknowledge from data link layer. This signal
serves as the acknowledge signal for the global request from
the transaction layer when accepting a transaction layer packet
from the data link layer.
Transmit data requested from data link layer. This is a
sequencing signal that makes a request for next data from the
transaction layer.
Transmit nullify transaction layer packet request. This signal is
asserted by the transaction layer in order to nullify a transmitted
transaction layer packet.
Transmit virtual channel arbitration result. This signal reports
arbitration results of the transaction layer packet that is currently
being transmitted.
Transmit sequencing valid. This signal, which depends on the
number of initialized lanes on the link, is a sequencing signal
pulse that enables data transfer from the transaction layer to the
data link layer.
Power management state machine. This signal indicates the
power management state machine encoding responsible for
scheduling the transition to legacy low power:
●
●
●
●
●
●
●
●
●
●
0000b: l0_rst
0001b: l0
0010b: l1_in0
0011b: l1_in1
0100b: l0_in
0101b: l0_in_wt
0110b: l2l3_in0
0111b: l2l3_in1
1000b: l2l3_rdy
others: reserved
and
rx_fval_tlp
. This 24-bit signal reports the requester ID
rx_ok_tlp
Description
PCI Express Compiler User Guide
test_out[37:0]
and
are asserted.
rx_ok_tlp
) are valid
are valid.
C–3
Related parts for IPR-PCIE/4
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE RENEW
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-XAUIPCS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: