IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 4
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Contents
Chapter 3. Specifications
Chapter 4. External PHYs
iv
PCI Express Compiler User Guide
Functional Description .......................................................................................................................... 3–1
Parameter Settings ............................................................................................................................... 3–31
Signals ................................................................................................................................................... 3–43
MegaCore Verification ........................................................................................................................ 3–94
External PHY Support ........................................................................................................................... 4–1
Selecting an External PHY .................................................................................................................. 4–15
External PHY Constraint Support ..................................................................................................... 4–16
Endpoint Types ................................................................................................................................ 3–2
Transaction Layer ............................................................................................................................. 3–2
Data Link Layer ................................................................................................................................ 3–7
Physical Layer ................................................................................................................................. 3–10
Analyzing Throughput .................................................................................................................. 3–11
Configuration Space Register Content ........................................................................................ 3–18
Active State Power Management (ASPM) .................................................................................. 3–22
Error Handling ............................................................................................................................... 3–24
Stratix GX PCI Express Compatibility ........................................................................................ 3–29
OpenCore Plus Time-Out Behavior ............................................................................................. 3–30
System Settings Page ..................................................................................................................... 3–31
Capabilities Page Parameters ....................................................................................................... 3–35
Buffer Setup Page ........................................................................................................................... 3–37
Power Management Page ............................................................................................................. 3–41
Transmit Interface Operation Signals .......................................................................................... 3–45
Receive Interface Operation Signals ............................................................................................ 3–61
Clocking ........................................................................................................................................... 3–72
Utility Signals .................................................................................................................................. 3–78
alt2gxb Support Signals ................................................................................................................. 3–89
Physical Layer Interface Signals ................................................................................................... 3–90
Simulation Environment ............................................................................................................... 3–94
Compatibility Testing Environment ............................................................................................ 3–94
16-bit SDR Mode ............................................................................................................................... 4–2
16-bit SDR Mode with a Source Synchronous TxClk .................................................................. 4–3
8-bit DDR Mode ................................................................................................................................ 4–5
8-bit DDR with a Source Synchronous TxClk .............................................................................. 4–6
8-bit SDR Mode ................................................................................................................................. 4–8
8-bit SDR with a Source Synchronous TxClk ............................................................................... 4–9
16-bit PHY Interface Signals ......................................................................................................... 4–11
8-bit PHY Interface Signals ........................................................................................................... 4–13
Using External PHYs With the Stratix GX Device Family ....................................................... 4–17
PCI Express Compiler Version 6.1
Altera Corporation
December 2006
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