IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 90
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Signals
Figure 3–13. 64-Bit Completion with Data Transaction of 8 DWORD Waveform
3–52
PCI Express Compiler User Guide
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Ideal Case Transmission
In the ideal case, the descriptor and data transfer are independent of each
other, and can even happen simultaneously. See
MegaCore function transmits a completion transaction of 8 DWORDS.
Address bit 2 is set to 0.
In clock cycle 4, the first data phase is acknowledged at the same time as
transfer of the descriptor.
1
PCI Express Compiler Version 6.1
2
X
X
3
CPLD
4
DW1
DW0
5
DW3
DW2
6
DW5
DW4
Clock Cycles
7
DW7
DW6
8
9
10
11
X
X
12
Figure
13
Altera Corporation
3–13. The
14
December 2006
15
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