IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 101

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IPTR-C2H-NIOS

Manufacturer Part Number
IPTR-C2H-NIOS
Description
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer
Altera
Datasheet

Specifications of IPTR-C2H-NIOS

Software Application
IP CORE, NIOS Processor And Functions
Core Architecture
Nios II
Features
ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
Core Sub-architecture
Cyclone
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Figure 4–2. Avalon-MM Master Port Resources
Altera Corporation
November 2009
memory, making it impossible for the accelerator to read both variables
on the same clock cycle. The C2H Compiler creates a single Avalon-MM
master port to access both values using interleaved accesses.
When memory accesses share a single Avalon-MM master port, the
reported data width is that of the largest data type being accessed. The
report shows each dereference operation for the shared Avalon-MM
master port resource. In
separate Avalon-MM master port resource because it resides in a different
memory than the input values.
For each dereference operation, the report shows the source line on which
the C statement appears. It also shows the variable being dereferenced,
and the data direction (read or write). Any one statement is either a read
Nios II C2H Compiler User Guide
9.1
Example 4–1
the pointer power requires a
Understanding the C2H View
4–7

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