IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 79

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 3–18. Early Scheduling of Read Operation with Latency
Altera Corporation
November 2009
The C2H Compiler optimizes the dependency graph for this function by
moving the read operation for ptr_in up to state 0. This optimization
allows the calculation of xy and xy_plus_z to occur during the two
cycles of latency required to fetch data for ptr_in.
Stalling
A state machine stalls when data needed for an operation is not available.
A state machine might stall while waiting for one or more of the following
actions to complete:
■
■
■
The state machine does not proceed until all reasons for stalling are
resolved.
Inner Loops
Each loop is implemented as a state machine, and an inner loop translates
to a particular state within the state machine for its containing function or
outer loop. In other words, an inner loop translates to a state machine
within a state machine. As the state machine for an inner loop executes,
the outer state machine stalls until the inner loop has completed.
Inner loop
Subfunction call
Memory transfer
9.1
C-to-Hardware Mapping Reference
Nios II C2H Compiler User Guide
3–39