IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 88
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IPTR-C2H-NIOS
Manufacturer Part Number
IPTR-C2H-NIOS
Description
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer
Altera
Datasheet
1.IPT-C2H-NIOS.pdf
(138 pages)
Specifications of IPTR-C2H-NIOS
Software Application
IP CORE, NIOS Processor And Functions
Core Architecture
Nios II
Features
ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
Core Sub-architecture
Cyclone
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Scheduling
Figure 3–25. Pipelined Loop Iterations Reading Memory with Latency
3–48
Nios II C2H Compiler User Guide
State 1 in
latency. The loop-carried dependencies on variables sum and list are
ideal cases, which do not impose restrictions on the pipeline scheduling.
Figure 3–25
iterations of the loop.
As shown in
of the loop immediately after the prior iteration completes State 0. At
Time 1, Iteration 1 starts a new read access from list, even though data
from list hasn't returned for Iteration 0. Due to the two cycles of read
latency, at any given time, there can be a maximum of two pending read
operations.
Over successive iterations of a loop, the C2H Compiler hides the memory
latency by pipelining the read transfers. Although multiple cycles of
latency are required to fill the pipeline, successive iterations can complete
at a rate of one per clock cycle, assuming no stalling occurs (see section
“Stalling” on page
Figure 3–24
illustrates how the C2H Compiler schedules successive
Figure
3–39).
3–25, the C2H Compiler is able to start a new iteration
remains empty because list has two cycles of read
9.1
Altera Corporation
November 2009
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