SM1211E915 Semtech, SM1211E915 Datasheet - Page 14

Dev Kit Accessory

SM1211E915

Manufacturer Part Number
SM1211E915
Description
Dev Kit Accessory
Manufacturer
Semtech
Datasheets

Specifications of SM1211E915

Modulation Type
FSK, OOK
Data Rate Max
200Kbps
Frequency Range
902MHz To 928MHz
Supply Voltage Range
2.1V To 3.6V
Module Interface
SPI
Supply Current
25mA
Accessory Type
RF Module
Sensitivity
-105dBm
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Package Type
TQFN EP
Operating Supply Voltage (min)
2.1V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Sensitivity (dbm)
-105dBm
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
The crystal oscillator (XO) forms the reference oscillator of an Integer-N Phase Locked Loop (PLL), whose
operation is discussed in the following section. Figure 5 shows a block schematic of the SX1211 PLL. Here the
crystal reference frequency and the software controlled dividers R, P and S determine the output frequency of the
PLL.
The VCO tank inductors are connected on an external differential input. Similarly, the loop filter is also located
externally. However, there is an internal 8pF capacitance at VCO input that should be subtracted from the desired
loop filter capacitance.
The output signal of the VCO is used as the input to the local oscillator (LO) generator stage, illustrated in Figure 6.
The VCO frequency is subdivided and used in a series of up (down) conversions for transmission (reception).
With an integer-N PLL architecture, the following criterion must be met to ensure correct operation:
Rev 7 – Sept 2
ADVANCED COMMUNICATIONS & SENSING
The comparison frequency, Fcomp, of the Phase Frequency Detector (PFD) input must remain higher than six
times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison
frequency Fcomp. This is expressed in the inequality:
However the PLLBW has to be sufficiently high to allow adequate PLL lock times
Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp≈100 kHz
which will ensure suitable PLL stability and speed.
3.2.3. PLL Architecture
3.2.4. PLL Tradeoffs
nd
, 2008
XT_M
VCO Output
XO
LO
XT_P
Figure 5: Frequency Synthesizer Description
÷(R
i
+1)
÷8
÷8
Fcomp
Figure 6: LO Generator
PLLBW
PFD
Page 14 of 92
Fcomp
90°
90°
90°
÷75.(P
6
LF_M
i
+1)+S
Vtune
Q
Q
I
I
Q
I
i
LO1 Rx
LO2 Rx
LO1 Tx
LO2 Tx
LF_P
VCO_M
Receiver
LOs
Transmitter
LOs
VCO_P
VR_VCO
LO
www.semtech.com
SX1211

Related parts for SM1211E915