AD5560JSVUZ-REEL Analog Devices Inc, AD5560JSVUZ-REEL Datasheet - Page 46

• Manufacturer Part Number: AD5560JSVUZ-REEL
• Description: 1.2A Programmable DPS With DACs
• Manufacturer: Analog Devices Inc
• Type: Power Supplyr

Specifications of AD5560JSVUZ-REEL

• Design Resources: Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
• Applications: Automatic Test Equipment
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5560
Table 19. DPS Register 2
Address
0x3
Default
0x0000
Bit
15
14
13
12
11
10
9
8
7
6:0
Name
SF0
SR[2:0]
GPO
SLAVE,
GANGIMODE
INT10K
Guard high-Z
Unused
Function
System force and sense line addressing, SF0. Bit SF0 addresses each of the different
combinations of switching the system force and sense lines to the force and sense pins at the
DUT.
Guard High-Z
(Bit 7)
0
0
1
1
Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp.
SR
0
1
2
3
4
5
6
7
General purpose output bit. The GPO bit can be used for any function, such as disconnecting
the decoupling capacitor to help speed up low current testing.
Ganging multiple devices increases the current drive available. Use these bits to enable
selection of the ganging mode and place the device in slave or master mode. In default
operation, each device is a master (gang of one). Figure
in this mode.
SLAVE
0
1
2
3
Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ
between the force and the sense lines (closes SW11). This resistor is actually made up of series
4 kΩ resistors followed by a 2 kΩ switch and another 4 kΩ resistor. There is a 10 kΩ resistor that
can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is
intended to maintain a force/sense connection when a DUT is not in place. It is not intended
to be connected when measurements are being made because this defeats the purpose of the
OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense
path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become
apparent when in high current ranges.
Set this bit high to high-Z the guard amplifier. This is required if using the GUARD/
SYS_DUTGND pin in the SYS_DUTGND function.
Set to 0.
Rev. C | Page 46 of 60
SFO
0
1
0
1
Action
1 V/μs
0.875 V/μs
0.75 V/μs
0.62 V/μs
0.5 V/μs
0.43 V/μs
0.35 V/μs
0.3125 V/μs
Action
Master: MASTER_OUT = internally connects to active EXTFORCE1/
EXTFORCE2 output
Master: MASTER_OUT = master MI
SLAVE FV to EXTFORCE1/EXTFORCE2 connected internally to close the
FVAMP loop
SLAVE FI
Data Bits, MSB First
SYS_SENSE Pin
Open
Sense
Open
Sense
SYS_FORCE Pin
Open
Force
Open
Force
shows how the device is configured
GUARD/SYS_DUTGND Pin
Guard
Guard
Open
DUTGND