AD6635BB Analog Devices Inc, AD6635BB Datasheet - Page 51

• Manufacturer Part Number: AD6635BB
• Description: IC,RF/Baseband Circuit,CMOS,BGA,324PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: AD6635r

Specifications of AD6635BB

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Current - Supply: 880mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 324-BGA
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

0x0D AGC A Signal Gain
This register is used to set the initial value for a signal gain used
in the gain multiplier. This 12-bit value sets the initial signal gain
between 0 dB and 96.296 dB in steps of 0.024 dB. 12-bit binary
floating-point representation is used with a 4-bit exponent
followed by an 8-bit mantissa. For example, 0111’10001001
is equivalent to 7
also be calculated as (7 + (137/256))
0x0E AGC A Loop Gain
This 8-bit register is used to define the open loop gain ‘K.’ Its
value can be set from 0 to 0.996 in steps of 0.0039. This
value of ‘K’ is updated in the AGC loop each time the AGC
is initialized.
0x0F AGC A Pole Location
This 8-bit register is used to define the open loop filter pole
location ‘P.’ Its value can be set from 0 to 0.996 in steps of
0.0039. This value of ‘P’ is updated in the AGC loop each time
the AGC is initialized. This open loop pole location will directly
impact the closed loop pole locations as explained in the AGC
Mode section.
0x10 AGC A Average Samples
This 6-bit register contains the scale used for the CIC filter and
the number of power samples to be averaged before being fed to
the CIC filter.
Bits 5–2 define the scale used for the CIC filter.
Bits 1–0 define the number of samples to be averaged before
they are sent to the CIC decimating filter. This number can be
set between 1 and 4, with bit representation 00 meaning one
sample and bit representation 11 meaning four samples.
0x11 AGC A Update Decimation
This 12-bit register sets the AGC decimation ratio from 1 to
4096. An appropriate scaling factor should be set to avoid loss
of bits.
0x12 AGC B Control Register
This 8-bit register controls features of the AGC A. The bits are
defined below:
Bits 7–5 define the output word length of the AGC. The output
word can be 4–8, 10, 12, or 16 bits wide. The control register
bit representation to obtain different output word lengths is
given in the Memory Map table (Table XV).
Bit 4 of this register sets the mode of operation for the AGC.
When this bit is 0, the AGC tracks to maintain the output sig-
nal level, and when this bit is 1, the AGC tracks to maintain a
constant clipping error. Consult the AGC Mode section for
more details about these modes.
Bits 3–1 are used to configure the synchronization of the AGC.
The CIC decimator filter in the AGC can be synchronized to an
external sync signal to output an update sample for the AGC
error calculation and filtering. This way the AGC gain changes
can be synchronized to an external block like a Rake receiver.
Whenever an external sync signal is received, the holdoff counter
at 0x0B is loaded and begins to count down. When the counter
reaches 1, the CIC filter dumps an update sample and starts
working toward a new update sample. The AGC can be initial-
ized on each SYNC, or on only the first SYNC.
Bit 3 is used to issue a command to the AGC to SYNC imme-
diately. If this bit is set, the CIC filter will update the AGC with
a new sample immediately and start operating towards the next
REV. 0
6.02 + 137
0.024 = 45.428 dB. It can
6.02 = 45.428 dB.
–51–
update sample. The AGC can be synchronized by the microport
control interface using this method.
Bit 2 is used to determine whether or not the AGC should
initialize on a SYNC. When this bit is set, the CIC filter is
cleared and new values for CIC decimation, number of averag-
ing samples, CIC scale, signal gain ‘Gs,’ gain ‘K,’ and pole
parameter ‘P’ are loaded. When Bit 2 = 0, the above-mentioned
parameters are not updated and the CIC filter is not cleared. In
both cases, an AGC update sample is output from the CIC
filter and the decimator starts operating toward the next output
sample whenever a SYNC occurs.
Bit 1 is used to ignore repetitive synchronization signals. In
some applications, the synchronization signal may occur peri-
odically. If this bit is clear, each synchronization request will
resynchronize the AGC. If this bit is set, only the first occur-
rence will cause the AGC to synchronize and will update AGC
gain values periodically, depending on the decimation factor of
the AGC CIC filter.
Bit 0 is used to bypass the AGC section, when it is set. When
bypassed, the 16 MSBs coming into the AGC section are
passed on to the output port (parallel/link). The output port
will further truncate the bit-width if 8-bit output is chosen.
0x13 AGC B Holdoff Counter
The AGC A Holdoff counter is loaded with the value written
to this address when either a Soft_SYNC or Pin_SYNC
comes into the channel. The counter begins counting down
so that when it reaches 1, a SYNC is given to AGC A. This
SYNC may or may not initialize the AGC, as defined by the
control word. The AGC loop is updated with a new sample
from the CIC filter whenever a SYNC occurs. If this register
is written to one, the AGC will be updated immediately when
the SYNC occurs. If this register is written to 0, the AGC
cannot be synchronized.
0x14 AGC B Desired Level
This 8-bit register contains the desired output power level or
desired clipping level, depending on the mode of operation.
This desired Request ‘R’ level can be set in dB from 0 dB to
–23.99 dB in steps of 0.094 dB. 8-bit binary floating-point
representation is used with a 2-bit exponent followed by a 6-bit
mantissa. The mantissa is in steps of 0.094 dB and the expo-
nent in 6.02 dB steps. For example 10’100101 represents 2
6.02 + 37
(2 + (37/64))
0x15 AGC B Signal Gain
This register is used to set the initial value for a signal gain
used in the gain multiplier. This 12-bit value sets the initial
signal gain between 0 dB and 96.296 dB in steps of
0.024 dB. 12-bit binary floating-point representation is used
with a 4-bit exponent followed by an 8-bit mantissa. For
example, 0111’10001001 is equivalent to 7
0.024 = 45.428 dB. It can also be calculated as (7 + (137/256))
0x16 AGC B Loop Gain
This 8-bit register is used to define the open loop gain ‘K.’ Its
value can be set from 0 to 0.996 in steps of 0.0039. This value of
‘K’ is updated in the AGC loop each time the AGC is initialized.
6.02 = 45.428 dB.
0.094 = 15.518 dB. It can also be calculated as
6.02 = 15.518 dB.
6.02 + 137
AD6635