AD7266BCPZ-REEL Analog Devices Inc, AD7266BCPZ-REEL Datasheet - Page 23

• Manufacturer Part Number: AD7266BCPZ-REEL
• Description: IC,Data Acquisition System,6-CHANNEL,12-BIT,LLCC,32PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7266BCPZ-REEL

• Design Resources: AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039)
• Number Of Bits: 12
• Sampling Rate (per Second): 2M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 33.6mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7266CBZ - BOARD EVALUATION FOR AD7266
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
The serial interface on the AD7266 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7266 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7266 TO ADSP-218x
The ADSP-218x family of DSPs interface directly to the
AD7266 without any glue logic required. The V
AD7266 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
its serial interface and therefore, the ADSP-218x, if necessary.
This example shows both D
connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Table 7 and Table 8.
Table 7. SPORT0 Control Register Setup
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
Table 8. SPORT1 Control Register Setup
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 0
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
Active low frame signal
Internal serial clock
Active low frame signal
External serial clock
Description
Alternate framing
Right justify data
16-bit data-word (or may be set to
1101 for 14-bit data-word)
Frame every word
Description
Alternate framing
Right justify data
16-bit data-word (or may be set to
1101 for 14-bit data-word)
Frame every word
OUT
A and D
OUT
B of the AD7266
DRIVE
pin of the
Rev. A | Page 23 of 28
The connection diagram is shown in Figure 43. The ADSP-218x
has the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1
tied together. TFS0 is set as an output, and both RFS0 and RFS1
are set as inputs. The DSP operates in alternate framing mode,
and the SPORT control register is set up as described. The
frame synchronization signal generated on the TFS is tied to
CS , and as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and,
under certain conditions, equidistant sampling may not be
achieved.
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and hence, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every one SCLK period. If the timer
registers are loaded with the value 803, then 100.5 SCLKs will
occur between interrupts and, subsequently, between transmit
instructions. This situation yields sampling that is not equidistant
as the transmit instruction is occurring on an SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7266
Figure 43. Interfacing the AD7266 to the ADSP-218x
D
D
V
1
SCLK
DRIVE
OUT
OUT
CS
A
B
SCLK0
SCLK1
TFS0
RFS0
RFS1
DR0
DR1
ADSP-218x
V
DD
AD7266
1