AD9773BSVRL Analog Devices Inc, AD9773BSVRL Datasheet - Page 29

• Manufacturer Part Number: AD9773BSVRL
• Description: IC,D/A CONVERTER,DUAL,12-BIT,CMOS,TQFP,80PIN
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9773BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9773-EBZ - BOARD EVALUATION AD9773

It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9773. This suffices unless the
input data rate is below 10 MHz, in which case an external series
RC is required between the LPF and CLKVDD pins.
POWER DISSIPATION
The AD9773 has three voltage supplies: DVDD, AVDD, and
CLKVDD. Figure 49, Figure 50, and Figure 51 show the current
required from each of these supplies when each is set to the
3.3 V nominal specified for the AD9773. Power dissipation (P
can easily be extracted by multiplying the given curves by 3.3.
As Figure 49 shows, I
rate, the interpolation rate, and the activation of the internal
digital modulator. I
modulation rate by itself. In Figure 50, I
type of sensitivity to the data, the interpolation rate, and the
modulator function but to a much lesser degree (<10%). In
Figure 51, I
only a small percentage of the overall AD9773 supply current
requirements.
400
350
300
250
200
150
100
50
0
0
Figure 49. I
CLKVDD
Figure 48. PLL_LOCK Output Signal (Pin 8) in the
8×, (MOD. ON)
Process of Locking (Typical Lock Time)
DVDD
8×
varies over a wide range yet is responsible for
50
DVDD
vs. f
DVDD
, however, is relatively insensitive to the
DATA
4×
is very dependent on the input data
vs. Interpolation Rate, PLL Disabled
f
DATA
4×, (MOD. ON)
100
(MHz)
AVDD
2×, (MOD. ON)
150
shows the same
1×
2×
200
Rev. D | Page 29 of 60
D
)
SLEEP/POWER-DOWN MODES
(Control Register 00h, Bit 3 and Bit 4)
The AD9773 provides two methods for programmable
reduction in power savings. The sleep mode, when activated,
turns off the DAC output currents but the rest of the chip
remains functioning. When coming out of sleep mode, the
AD9773 immediately returns to full operation. Power-down
mode, on the other hand, turns off all analog and digital
circuitry in the AD9773 except for the SPI port. When
returning from power-down mode, enough clock cycles must
be allowed to flush the digital filters of random data acquired
during the power-down cycle.
76.0
75.5
75.0
74.5
74.0
73.5
73.0
72.5
72.0
35
30
25
20
15
10
5
0
Figure 51. I
0
0
Figure 50. I
8×, (MOD. ON)
CLKVDD
AVDD
8×
50
50
vs. f
8 ×
vs. f
DATA
DATA
4 ×
4×
vs. Interpolation Rate, PLL Disabled
f
f
vs. Interpolation Rate, PLL Disabled
DATA
DATA
100
100
(MHz)
(MHz)
4×, (MOD. ON)
150
150
2×, (MOD. ON)
2 ×
1×
1 ×
2×
AD9773
200
200