AD9779A-EBZ Analog Devices Inc, AD9779A-EBZ Datasheet - Page 45

• Manufacturer Part Number: AD9779A-EBZ
• Description: Dual 16B, 1.0 GSPS TxDAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9779A-EBZ

• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9779A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE SYNCHRONIZATION
System demands can impose two different requirements for
synchronization. Some systems require multiple DACs to be
synchronized to each other. This is the case when supporting
transmit diversity or beam forming, where multiple antennas
are used to transmit a correlated signal. In this case, the DAC
outputs need to be phase aligned with each other, but there may
not be a requirement for the DAC outputs to be aligned with a
system level reference clock. In systems with a time division
multiplexing transmit chain, one or more DACs may need to be
synchronized with a system level reference clock. The options
for synchronizing devices under these two conditions are
described in the following section.
SYNCHRONIZATION LOGIC OVERVIEW
Figure 88 shows the block diagram of the on-chip synchroniza-
tion logic. The basic operation of the synchronization logic is to
generate a single DACCLK cycle wide initialization pulse that
sets the clock generation state machine logic to a known state.
This initialization pulse loads the clock generation state machine
with the Clock State<4:0> value as its next state. If the initializa-
tion pulse from the synchronization logic is generated properly,
it is active for one DAC clock cycle, every 32 DAC clock cycles.
Because the clock generation state machine has 32 states operating
at the DACCLK rate, every initialization pulse received after the
first pulse loads the state in which the state machine is already
in, maintaining proper clocking operation of the device.
Nominally, the SYNC_I input should have one rising edge every
32 (or multiple of 32) clock cycles to maintain proper synchro-
nization. The pulse generation logic can be programmed to
suppress outgoing pulses if the incoming SYNC_I frequency is
above DACCLK/32. Extra pulses can be suppressed by the ratios
listed in Table 27. The SYNC_I frequency can be lower than
DACCLK/32 as long as output pulses are generated from the
GENERATION
MACHINE
CLOCK
NO MINIMUM FREQUENCY
STATE
SYNC_I
MIN 1 DACCLK CYCLE
DUTY CYCLE
FREQUENCY
MAX
Figure 88. Synchronization Circuitry Block Diagram
MAX 50%
LOAD DACCLK OFFSET VALUE (REG 0x07),
[4:0], ONE DACCLK CYCLE/INCREMENT
f
DATA
DELAY REGISTER
BIT 0 (1× INTERPOLATION)
(REG 0x06),
BIT 1 (2×)
BIT 2 (4×)
BIT 3 (8×)
BIT 4 (8× WITH
ZERO STUFFING)
DACCLK
/2
DELAY
SYNC
[7:4]
BYPASS
ERROR DETECT
GENERATION
PLL
CIRCUITRY
MUX
PULSE
LOGIC
INTERNAL
PLL
SYNC IRQ
REFCLK
Rev. A | Page 45 of 60
pulse generation circuit on a multiple of 32 DACCLK periods.
In any case, the maximum frequency of SYNC_I must be less
than f
Table 27. Settings Required to Support Various SYNC_I
Frequencies
SYNC_I
Ratio<2:0>
000
001
010
011
100
101
110
111
As an example, if a SYNC_I signal with a frequency of f
is used, then both 011 and 100 are valid settings for the SYNC_I
Ratio<2:0> value. A setting of 011 results in one initialization
pulse being generated every 32 DACCLK cycles and a setting
of 100 results in one initialization pulse being generated every
64 DACCLK cycles. Both cases result in proper device
synchronization.
The Clock State<4:0> value is the state to which the clock
generation state machine resets upon initialization. By varying
this value, the timing of the internal clocks with respect to the
SYNC_I signal can be adjusted. Every increment of the Clock
State<4:0> value advances the internal clocks by one DACCLK
period.
Synchronization Timing Error Detection
The synchronization logic has error detection circuitry similar
to the input data timing. The SYNC_I Timing Margin<3:0>
variable determines how much setup and hold margin the
synchronization interface needs for the SYNC_I timing error
IRQ to remain inactive (show error free operation). Therefore,
the SYNC_I timing error IRQ is set whenever the setup and
hold margins drop below the SYNC_I Timing Margin<3:0>
value and does not necessarily indicate that the SYNC_I input
was latched incorrectly.
When a SYNC_I timing error IRQ is set, corrective action can
be taken to restore timing margin. One course of action is to
temporarily reduce the timing margin until the SYNC_I timing
error is cleared. Then increase the SYNC_I delay by two incre-
ments. Check whether the timing margin has increased or
decreased. If it has increased, continue incrementing the value
of SYNC_I delay until the margin is maximized. If incrementing
the SYNC_I delay reduced the timing margin, then the delay
should be reduced until the timing margin is optimized.
DACCLK
.
AD9776A/AD9778A/AD9779A
SYNC_I Rising Edges Required for
Synchronization Pulse
1 (default)
2
4
8
16
Invalid setting
Invalid setting
Invalid setting
DACCLK
/4